JP2007317740A - 配線基板及びその製造方法ならびに半導体装置 - Google Patents
配線基板及びその製造方法ならびに半導体装置 Download PDFInfo
- Publication number
- JP2007317740A JP2007317740A JP2006143172A JP2006143172A JP2007317740A JP 2007317740 A JP2007317740 A JP 2007317740A JP 2006143172 A JP2006143172 A JP 2006143172A JP 2006143172 A JP2006143172 A JP 2006143172A JP 2007317740 A JP2007317740 A JP 2007317740A
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- Prior art keywords
- protruding electrode
- adhesive layer
- conductor wiring
- wiring
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000000758 substrate Substances 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims description 51
- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 239000004020 conductor Substances 0.000 claims abstract description 173
- 239000000463 material Substances 0.000 claims abstract description 50
- 239000012790 adhesive layer Substances 0.000 claims description 115
- 239000010410 layer Substances 0.000 claims description 64
- 238000000034 method Methods 0.000 claims description 17
- 238000009713 electroplating Methods 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 10
- 239000000853 adhesive Substances 0.000 claims description 6
- 230000001070 adhesive effect Effects 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 6
- 238000003825 pressing Methods 0.000 claims description 4
- 238000007747 plating Methods 0.000 description 22
- 239000010949 copper Substances 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- 238000001039 wet etching Methods 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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- H05K3/4007—Surface contacts, e.g. bumps
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Abstract
【解決手段】絶縁性基材2と、絶縁性基材の表面に形成された接着層3と、接着層の表面に形成された導体配線4と、導体配線の長手方向を横切って導体配線の両側の接着層上の領域に亘り形成された突起電極5とを備える。突起電極が表面に形成された領域の導体配線の裏面と、突起電極における導体配線の両側の接着層上に形成された領域の裏面および側面の一部が、接着層の表面から内部に向かって沈み込み接着層と接着されている。
【選択図】図2
Description
図1は、本発明の第1の実施形態における配線基板1を示す平面図であり、図2は図1のA−A’断面図である。
本発明の第2の実施形態における配線基板の一例は、上述の図2の断面図に示した構成を有する。
図3は、本発明の第3の実施形態における配線基板1を示す断面図である。図3において、2は絶縁性基材、3は接着層、4は導体配線、5は突起電極であり、これらは第1の実施形態と同一である。6は突起電極5を被覆する第1の導電層であり、第1の導電層6を介して、突起電極5の裏面及び側面と接着層3とが接着されている。
図4は、本発明の第4の実施形態による半導体装置を示す断面図である。図4において、配線基板1は第3の実施形態と同一であり、絶縁性基材2、接着層3、導体配線4、突起電極5、および第1の導電層6から構成されている。7は配線基板1にフェイスダウン実装された半導体素子であり、半導体素子7上には電極パッド8及び電極パッドの表面を被覆する第2の導電層9が形成されており突起電極5と第1の導電層6を介して接合されている。
本発明の第5の実施形態における配線基板の製造方法について、図面を参照しながら説明する。図5〜図9は、図1〜図3に示した配線基板1を製造する工程を工程順に示す。
図1〜図3に示した配線基板1と同一の構成要素については同一の参照番号を付して説明の繰返しを省略する。
本発明の第6の実施形態における半導体装置の製造方法について、図面を参照しながら説明する。
2、22 絶縁性基材
3 接着層
4、23 導体配線
5、5a、5b、24 突起電極
6、25 第1の導電層
7、26 半導体素子
8、27 電極パッド
9、28 第2の導電層
10 Cu箔
11 レジスト
12 開口部
13 加熱ツール
14 ステージ
Claims (15)
- 絶縁性基材と、
前記絶縁性基材の表面に形成された接着層と、
前記接着層の表面に形成された導体配線と、
前記導体配線の長手方向を横切って前記導体配線の両側の前記接着層上の領域に亘り形成された突起電極とを備えた配線基板において、
前記突起電極が表面に形成された領域の前記導体配線の裏面と、前記突起電極における前記導体配線の両側の前記接着層上に形成された領域の裏面および側面の一部が、前記接着層の表面から内部に向かって沈み込み前記接着層と接着されていることを特徴とする配線基板。 - 前記導体配線の長手方向を横切って前記導体配線の両側の前記接着層上の領域に亘り形成された突起電極の幅が前記導体配線の裏面の幅よりも広く、かつ前記突起電極の側面と前記導体配線の裏面とが前記突起電極の裏面を経由して凸形状に滑らかに接続された形状を有する請求項1に記載の配線基板。
- 前記絶縁性基材の表面に形成された接着層の厚みが、前記突起電極が表面に形成された前記導体配線の裏面と、前記突起電極における前記導体配線の両側の前記接着層上に形成された領域の裏面および側面の一部が、前記接着層の表面から内部に向かって沈み込みこむ距離よりも厚い請求項1または2に記載の配線基板。
- 前記突起電極における前記突起電極の表面及び前記導体配線の両側の前記接着層上に形成された領域が、前記突起電極とは異なる一つ以上の材質から構成された第1の導電層で被覆されている請求項1〜3のいずれか1項に記載の配線基板。
- 前記突起電極における前記接着層の表面から内部に向かって沈み込んだ領域の側面が、前記第1の導電層を介して前記接着層と接着されている請求項4に記載の配線基板。
- 少なくとも表面が接着性を有する絶縁性基材と、
前記絶縁性基材の表面に形成された導体配線と、
前記導体配線の長手方向を横切って前記導体配線の両側の前記絶縁性基材上の領域に亘り形成された突起電極とを備えた配線基板において、
前記突起電極が表面に形成された領域の前記導体配線の裏面と、前記突起電極における前記導体配線の両側の前記絶縁性基材上に形成された領域の裏面および側面の一部が、前記絶縁性基材の表面から内部に向かって沈み込み前記絶縁性基材と接着されていることを特徴とする配線基板。 - 前記導体配線の長手方向を横切って前記導体配線の両側の前記絶縁性基材上の領域に亘り形成された突起電極の幅が前記導体配線の裏面の幅よりも広く、かつ前記突起電極の側面と前記導体配線の裏面とが前記突起電極の裏面を経由して凸形状に滑らかに接続された形状を有する請求項6に記載の配線基板。
- 前記突起電極における前記突起電極の表面及び前記導体配線の両側の前記絶縁性基材上に形成された領域が、前記突起電極とは異なる一つ以上の材質から構成された第1の導電層で被覆されている請求項6または7に記載の配線基板。
- 前記突起電極における前記絶縁性基材の表面から内部に向かって沈み込んだ領域の側面が、前記第1の導電層を介して前記絶縁性基材と接着されている請求項8に記載の配線基板。
- 請求項1〜9のいずれか1項に記載の配線基板と、前記配線基板上に搭載された半導体チップとを備え、前記半導体チップの電極パッドと前記配線基板に形成された突起電極とが電気的に接続された半導体装置。
- 前記電極パッドの表面に前記電極パッドとは異なる一つ以上の材質から構成される第2の導電層を備えた請求項10に記載の半導体装置。
- 絶縁性基材上に接着層を備え、前記接着層上に導体層が積層されている積層基材を準備する工程と、
前記積層基材の表面の前記導体層をパターンニングして導体配線を形成する工程と、
前記導体配線を陰極とする電解めっきにより前記導体配線の長手方向を横切って前記導体配線の両側の前記接着層上の領域に亘り突起電極を形成する工程と、
前記突起電極を上面から加熱加圧し、前記突起電極の下の前記導体配線の裏面と前記突起電極における前記導体配線の両側の前記接着層上に形成された領域の裏面と側面の一部を、前記接着層の表面から内部に向かって沈み込ませ前記接着層と接着する工程とを備えた配線基板の製造方法。 - 前記導体配線を陰極とする電解めっきにより前記導体配線の長手方向を横切って前記導体配線の両側の前記接着層上の領域に亘り突起電極を形成する工程の後に、
前記突起電極の表面及び前記突起電極における前記導体配線の両側の前記接着層上に形成された領域を、前記突起電極とは異なる一つ以上の材質から構成される導電層で被覆する工程を備え、
前記導電層で被覆した突起電極を上面から加熱加圧し、前記突起電極における前記導体配線の両側の前記接着層上に形成された領域の裏面と側面の一部を、前記接着層の表面から内部に向かって沈み込ませ前記導電層を介して前記接着層と接着する請求項12に記載の配線基板の製造方法。 - 絶縁性基材上に接着層を備え、前記接着層上に導体層が積層されている積層基材を準備する工程と、
前記積層基材の表面の前記導体層をパターンニングして導体配線を形成する工程と、
前記導体配線を陰極とする電解めっきにより前記導体配線の長手方向を横切って前記導体配線の両側の前記接着層上の領域に亘り、前記導体配線を陰極とする電解めっきにより突起電極を形成する工程と、
前記突起電極の表面及び前記突起電極における前記導体配線の両側の前記接着層上に形成された領域を、前記突起電極とは異なる材質からなる導電層で被覆する工程と、
前記突起電極と相対する位置に電極パッドを備えた半導体チップを準備する工程と、
前記半導体チップの前記電極パッドと前記突起電極とを相対させ載置し、前記半導体チップの裏面から加熱加圧して前記電極パッドと前記突起電極の表面の導電層とを加熱圧着させると同時に、前記突起電極における前記導体配線の両側の前記接着層上に形成された領域の裏面と側面の一部を、前記接着層の表面から内部に向かって沈み込ませ前記導電層を介して前記接着層と接着する工程とを備えた半導体装置の製造方法。 - 前記半導体チップの裏面から加熱加圧する工程と同時に超音波振動を加える請求項14記載の半導体装置の製造方法。
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Also Published As
Publication number | Publication date |
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US7847198B2 (en) | 2010-12-07 |
JP4813255B2 (ja) | 2011-11-09 |
TW200802633A (en) | 2008-01-01 |
US20070284738A1 (en) | 2007-12-13 |
KR20070113112A (ko) | 2007-11-28 |
CN101079407A (zh) | 2007-11-28 |
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