CN101079407A - 布线基板及其制造方法以及半导体器件 - Google Patents

布线基板及其制造方法以及半导体器件 Download PDF

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Publication number
CN101079407A
CN101079407A CNA2007101041992A CN200710104199A CN101079407A CN 101079407 A CN101079407 A CN 101079407A CN A2007101041992 A CNA2007101041992 A CN A2007101041992A CN 200710104199 A CN200710104199 A CN 200710104199A CN 101079407 A CN101079407 A CN 101079407A
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mentioned
conductor wiring
projected electrode
adhesive linkage
zone
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CNA2007101041992A
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下石坂望
中村嘉文
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Publication of CN101079407A publication Critical patent/CN101079407A/zh
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Abstract

本发明的布线基板，包括：绝缘性基材(2)；在绝缘性基材的表面上形成的粘接层(3)；在粘接层的表面上形成的导体布线(4)；横截导体布线的长度方向并遍及导体布线两侧的粘接层上的区域而形成的突起电极(5)。形成有突起电极的区域的导体布线的背面和突起电极中的在导体布线两侧的粘接层上形成的区域的背面及侧面的一部分，从粘接层的表面向内部凹陷，与粘接层粘接。即使导体布线的布线宽度减少，也能够将导体布线牢固地粘接在布线基板上。

Description

布线基板及其制造方法以及半导体器件
技术领域
本发明涉及一种形成有突起电极的布线基板及其制造方法、以及使用该布线基板的半导体器件。
背景技术
众所周知一种半导体器件，通过在液晶用等半导体器件中多采用的TAB(卷带式自动接合，Tape Automated Bonding)工艺，利用具有突起电极的布线基板，在布线基板上面朝下地安装半导体元件，布线基板的突起电极和半导体元件上的电极焊盘被接合(例如，参照US2004/0212969A1)。
下面，参照附图，说明现有例的具有突起电极的布线基板和使用布线基板的半导体器件。图8是表示现有的布线基板21的平面图，图9是图8的B-B′截面图。
在图8、图9中，22是绝缘性基材，23是在绝缘基材22的表面上形成的导体布线。在导体布线23的前端部形成有突起电极24。25是覆盖导体布线23和突起电极24的表面的第1导电层，通过电解镀Au、电解镀Ni/Au或非电解镀Sn等形成。
在用于TAB工艺中的封装中使用的布线基板，绝缘性基材等采用具备可挠性的材料和结构，通过卷带(reel to reel)方式连续地进行布线基板的供给、向布线基板的半导体元件的安装、半导体元件安装后的检测工序等。为了使布线基板具备可挠性，作为绝缘性基材22使用厚度从12μm到40μm左右的由聚酰亚胺等形成的柔性带。通过湿法刻蚀，对厚度9μm～18μm左右的Cu箔进行构图而形成绝缘性基材22上的导体布线23。通过湿法刻蚀形成导体布线23时，从导体布线23的上表面向下方及横方向进行刻蚀，所以导体布线23的截面形状如图9所示地成为锥形形状。例如，在导体布线23的间距为40μm时，使用厚度9μm的Cu箔进行湿法刻蚀以使导体布线23的底部的宽度成为15μm的情况下，导体布线23的上面部的宽度大致成为8μm。突起电极24横截导体布线23的长度方向并遍及导体布线23的两侧的区域，通过电解铜电镀，形成为厚度8μm、宽度20μm左右。
图10是表示一面对半导体元件26进行加热加压一面将其面朝下安装在上述现有例的布线基板21上而得到的半导体器件的截面图。在半导体元件26上形成有电极焊盘27，覆盖电极焊盘27的表面而形成有第2导电层28。第2导电层28通过第1导电层25与布线基板21上的突起电极24接合。通过电解镀Au和无电解镀Ni/Au等形成第2导电层28。
近年来，使用TAB工艺的液晶用半导体元件，进行基于液晶面板的大型化、高精度化的多插脚化，根据用途还出现在大小20mm×1mm左右的半导体芯片中具备超过1000焊盘的电极焊盘的半导体元件。为此，正推进电极焊盘的窄间距化，要求间距为40μm以下。
但是，在图10所示的使用了现有的布线基板21的半导体器件中，仅导体布线23的底面与绝缘性基材22的表面粘接，另一方面，虽然突起电极25的底面通过电解电镀与绝缘性基材22的表面接触进行生长，但没有粘接。因此，对应于电极焊盘27的窄间距化使导体布线23的布线宽度减少时，导体布线23和绝缘性基材22的粘接强度下降。为此，存在这样的课题，即，由于面朝下安装半导体元件26之后的热应力、和作为TAB工艺特点的卷带式搬运时的布线基板21的弯曲等导致的机械的应力，使导体布线23从绝缘性基材22上剥离。
发明内容
本发明用于解决上述现有的课题，其目的在于，提供一种即使导体布线的布线宽度减少也能够将导体布线牢固地粘接在布线基板上的布线基板。
为了实现上述目的，本发明的第1结构的布线基板，包括：绝缘性基材，在上述绝缘性基材的表面上形成的粘接层，在上述粘接层的表面上形成的导体布线，横截上述导体布线的长度方向并遍及上述导体布线两侧的上述粘接层上的区域形成的突起电极；形成有上述突起电极的区域的上述导体布线的背面和上述突起电极中的在上述导体布线两侧的上述粘接层上形成的区域的背面及侧面的一部分，从上述粘接层的表面向内部凹陷，并与上述粘接层粘接。
此外，本发明的第2结构的布线基板，包括：至少表面具有粘接性的绝缘性基材，在上述绝缘性基材的表面上形成的导体布线，横截上述导体布线的长度方向并遍及上述导体布线两侧的上述绝缘性基材上的区域而形成的突起电极；形成有上述突起电极的区域的上述导体布线的背面、和在上述突起电极中的上述导体布线两侧的上述绝缘性基材上形成的区域的背面及侧面的一部分，从上述绝缘性基材的表面向内部凹陷，并与上述绝缘性基材粘接。
本发明的布线基板的制造方法，包括：准备在绝缘性基材上具备粘接层并在上述粘接层上层叠了导体层的层叠基材的工序；对上述层叠基材的表面的上述导体层进行构图而形成导体布线的工序；通过将上述导体布线作为阴极的电解电镀，横截上述导体布线的长度方向并遍及上述导体布线两侧的上述粘接层上的区域而形成突起电极的工序；从上面对上述突起电极加热加压，使上述突起电极之下的上述导体布线的背面和上述突起电极中的在上述导体布线两侧的上述粘接层上形成的区域的背面和侧面的一部分，从上述粘接层的表面向内部凹陷，并与上述粘接层粘接的工序。
本发明的半导体器件的制造方法，包括：准备在绝缘性基材上具备粘接层并在上述粘接层上层叠了导体层的层叠基材的工序；对上述层叠基材的表面的上述导体层进行构图而形成导体布线的工序；通过将上述导体布线作为阴极的电解电镀，横截上述导体布线的长度方向并遍及上述导体布线两侧的上述粘接层上的区域而形成突起电极的工序；将上述突起电极的表面及上述突起电极中的在上述导体布线两侧的上述粘接层上形成的区域，利用由与上述突起电极不同的材质形成的导电层来覆盖工序；准备在与上述突起电极相对的位置具备电极焊盘的半导体芯片的工序；使上述半导体芯片的上述电极焊盘和上述突起电极相对放置，从上述半导体芯片的背面进行加热加压，使上述电极焊盘和上述突起电极的表面的导电层加热压接的同时，使上述突起电极中的在上述导体布线两侧的上述粘接层上形成的区域的背面和侧面的一部分，从上述粘接层的表面向内部凹陷，通过上述导电层与上述粘接层粘接的工序。
附图说明
图1是表示本发明的第1及第2实施方式的布线基板的平面图。
图2是表示同一布线基板的A-A′截面的截面图。
图3是表示本发明的第3实施方式的布线基板的截面图。
图4是表示本发明的第4实施方式的半导体器件的截面图。
图5A～图5G是表示本发明的第5实施方式的布线基板的制造方法的截面图。
图6是表示该制造方法的平面图。
图7A～图7B是表示本发明的第6实施方式的半导体器件的制造方法的截面图。
图8是表示现有例的布线基板的平面图。
图9是表示该布线基板的B-B′截面的截面图。
图10是表示使用现有例的布线基板的半导体器件的截面图。
具体实施方式
根据本发明的布线基板，具有这样的结构，即，横截导体布线的长度方向并遍及导体布线两侧的粘接层上或具有粘接性的绝缘基材上的区域形成的突起电极，从粘接层或绝缘性基材的表面向内部凹陷，除导体布线的背面以外，突起电极的背面和侧面的一部分也与粘接层或绝缘性基材粘接。由此，即使导体布线的布线宽度减少，突起电极也牢固地粘接在布线基板上。
此外，根据本发明的布线基板的制造方法或半导体器件的制造方法，通过将导体布线作为阴极的电解电镀形成突起电极，从而能够具有使突起电极的宽度比导体布线的背面的宽度宽，并且，突起电极侧面和导体布线的背面经由突起电极的背面以凸形形状平滑地连接的形状。由此，能够扩大突起电极和粘接层的粘接面积，使其牢固地粘接在布线基板上。
在上述结构的本发明的第1结构的布线基板中，优选上述突起电极的宽度比上述导体布线的背面的宽度更宽，并且，从上述导体布线的背面经由上述突起电极到达突起电极侧面的区域的面以凸形形状平滑地形成。
此外，优选形成在上述绝缘性基材的表面上的粘接层的厚度，比形成有上述突起电极的区域的上述导体布线的背面和上述突起电极中的在上述导体布线两侧的上述粘接层上形成的区域的背面及侧面的一部分从上述粘接层表面向内部凹陷的距离厚。
此外，优选上述突起电极中的上述突起电极的表面及在上述导体布线两侧的上述粘接层上形成的区域，被由不同于上述突起电极的一种以上材质构成的第1导电层覆盖。
此外，优选从上述突起电极中的上述粘接层的表面向内部凹陷的区域的侧面，通过上述第1导电层与上述粘接层粘接。
在上述结构的本发明的第2结构的布线基板中，优选具有如下形状：横截上述导体布线的长度方向并遍及上述导体布线两侧的上述绝缘性基材上的区域而形成的突起电极的宽度比上述导体布线的背面的宽度宽，并且，上述突起电极侧面和上述导体布线的背面经由上述突起电极的背面以凸形形状平滑地被连接。
此外，优选上述突起电极中的上述突起电极的表面及在上述导体布线两侧的上述绝缘性基材上形成的区域，被由不同于上述突起电极的一种以上材质构成的第1导电层覆盖。
此外，优选上述突起电极中的从上述绝缘性基材的表面向内部凹陷的区域的侧面，通过上述第1导电层与上述绝缘性基材粘接。
本发明的半导体器件，包括上述任意结构的布线基板和在上述布线基板上装载的半导体芯片，上述半导体芯片的电极焊盘和形成在上述布线基板上的突起电极电连接。
在上述结构中，优选在上述电极焊盘表面具备由与上述电极焊盘不同的一种以上材质构成的第2导电层。
在上述结构的本发明的布线基板的制造方法中，优选通过将上述导体布线作为阴极的电解电镀，横截上述导体布线的长度方向并遍及上述导体布线两侧的上述粘接层上的区域而形成突起电极的工序之后；具备将上述突起电极的表面及上述突起电极中的在上述导体布线两侧的上述粘接层上形成的区域，利用由与上述突起电极不同的一种以上材质构成的导电层来覆盖的工序；从上面对由上述导电层覆盖的突起电极进行加热加压，使上述突起电极中的在上述导体布线两侧的上述粘接层上形成的区域的背面和侧面的一部分，从上述粘接层的表面向内部凹陷，通过上述导电层与上述粘接层粘接。
在上述结构的本发明的半导体器件的制造方法中，优选与从半导体芯片的背面进行加热加压的工序同时施加超声波振动。
下面，参照附图，说明本发明的实施方式。
(第1实施方式)
图1是表示本发明的第1实施方式的布线基板1的平面图，图2是表示图1的A-A′的截面图。
在图1、图2中，2是绝缘性基材，2是在绝缘性基材2的表面上形成的粘接层，4是在粘接层3上形成的导体布线。横截导体布线4的前端部的长度方向，遍及导体布线4的两侧的粘接层3上的区域形成有突起电极5。如图2所示，形成有突起电极5的区域的导体布线4的背面和突起电极5中的在导体布线4的两侧的粘接层3上形成的区域的背面及侧面的一部分从粘接层3的表面向内部凹陷，与粘接层3粘接。
在此，作为绝缘性基材2使用厚度从12μm到40μm左右的由聚酰亚胺等制成的柔性带。绝缘性基材2上的粘接层3由环氧树脂等形成，厚度为3μm～10μm左右。通过湿法刻蚀对厚度9μm～18μm左右的Cu箔进行构图而形成导体布线4。通过湿法刻蚀形成导体布线4的情况下，由于从导体布线4的上部向下方及横方向进行刻蚀，所以导体布线4的截面形状如图2所示为锥形形状。通过镀Cu形成突起电极5，导体布线4和突起电极5的宽度和高度由绝缘性和加工精度、机械强度来决定。例如，导体布线4的间距为40μm时，使用厚度9μm的Cu箔，进行湿法刻蚀使导体布线4的下部的宽度成为15μm。此情况下，导体布线4的上部的宽度大致为8μm左右。在导体布线4上通过电解镀铜将突起电极5形成为厚度8μm、宽度20μm左右。
希望将粘接层3的厚度形成得比形成有突起电极5的区域的导体布线4的背面和突起电极5中的在导体布线4的两侧的粘接层3上形成的区域的背面及侧面的一部分从粘接层3的表面向内部凹陷的距离厚。
再有，在此作为突起电极5的材料使用Cu，作为具有导电性的材料，也可以使用Au和Ni、In等。
此外，取代在绝缘性基材2的表面形成有粘接层3的结构，也可以是绝缘性基材2的至少表面具备粘接性的结构。在下面的实施方式中也相同。
如上所述，根据本发明的第1实施方式，形成有突起电极5的区域的导体布线4的背面和突起电极5中的在导体布线4的两侧的粘接层3上形成的区域的背面及侧面的一部分，从粘接层3的表面向内部凹陷并与粘接层3粘接。因此，与仅导体布线4的背面和粘接层3粘接的情况相比，能够提高导体布线4和粘接层3的粘接强度。
(第2实施方式)
本发明的第2实施方式中的布线基板具有在上述图2中以截面图表示的结构。
在图2的截面图中，横截导体布线4的长度方向并遍及导体布线4的两侧的粘接层3上的区域而形成的突起电极5的宽度比导体布线4的背面的宽度宽，并且从导体布线4的背面经由突起电极5的背面而到达突起电极5的侧面的区域的面以凸形形状平滑地被形成。突起电极5的背面及侧面的一部分从粘接层3的表面向内部凹陷且与粘接层3粘接。
根据第2实施方式，在突起电极5的侧面和粘接层3之间不产生间隙而使突起电极5的背面和侧面连续地密接在粘接层上，所以能够提高突起电极5和粘接层3的粘接强度。
(第3实施方式)
图3是表示本发明的第3实施方式中的布线基板1的截面图。在图3中，绝缘性基材2、粘接层3、导体布线4及突起电极5与第1实施方式相同。并且，设置有覆盖突起电极5的第1导电层6，通过第1导电层6粘接突起电极5的背面及侧面和粘接层3。
在此，作为第1导电层6，例如通过电解镀Au形成0.3μm～2μm左右的厚度。此外，考虑第1导电层6的势垒性和材料，以0.5μm左右的厚度形成Au。此外，第1导电层6也可以是由多种材料形成的结构，例如也可以底层为1μm左右的Ni，表层为0.5μm左右的Au。此外，也可替代电解电镀通过非电解电镀形成第1导电层6。
根据此第3实施方式，由于通过第1导电层6使突起电极5的背面及侧面与粘接层3粘接，所以第1导电层6成为势垒，能够防止突起电极5的材料向粘接层3扩散，可以提高布线基板1的绝缘可靠性。
(第4实施方式)
图4是表示本发明的第4实施方式的半导体器件的截面图。在图4中，布线基板1和第3实施方式相同，由绝缘性基材2、粘接层3、导体布线4、突起电极5及第1导电层6构成。7是面朝下安装在布线基板1上的半导体元件。在半导体元件7上形成有电极焊盘8，覆盖电极焊盘8的表面形成有第2导电层9。第2导电层9通过第1导电层6与突起电极5接合。
例如，通过电解镀Au和非电解镀Ni/Au等形成第2导电层9。作为一个例子，形成4μm非电解镀Ni后，形成0.1μm左右的非电解镀Au。
根据此第4实施方式，形成有突起电极5的区域的导体布线4的背面、用突起电极5中的在导体布线4的两侧的粘接层3上形成的区域的背面和侧面的一部分从粘接层3的表面向内部凹陷，并与粘接层3粘接。因此，与仅导体布线4的背面粘接在粘接层3的情况相比，提高导体布线4和粘接层3的粘接强度。因此，由于面朝下安装半导体元件7后的热的应力或由TAB工艺的特征即卷带搬运时的布线基板1的弯曲等导致的机械应力，而使导体布线4和突起电极5从布线基板1上剥离的情况被抑制。
(第5实施方式)
参照附图，说明本发明的第5实施方式的布线基板的制造方法。图5A～图5G按工序顺序表示制造图1～图3所示的布线基板的工序。图6是表示图5B和图5C之间的工序的平面图。对于与图1～图3中示出的布线基板1相同的构成要素赋予相同的参照编号省略重复的说明。
图5A是制造布线基板1的工序的中途沿图1的A-A′线的截面图，示出了与粘接层3粘接的Cu箔10。在图6的平面图中，11表示在布线基板1上的整个面上形成的抗蚀剂，12表示抗蚀剂11的开口部。开口部12跨越多条导体布线4开口。图5B～图5F是与图5A同样位置的截面图。图5G也是表示同样位置的制造中途的布线基板的截面图，但是，在图5G中还示出了加热工具13和载物台14。
首先，如图5A所示，准备通过粘接层13粘接绝缘性基材2和Cu箔10的层叠基材。接着，如图5B所示，对Cu箔10进行湿法刻蚀形成导体布线4。此时，由于从导体布线4的上部向下方及横方向进行刻蚀，所以导体布线4的截面形状如图所示成为锥形形状。
接着，如图6所示，在形成了导体布线4的布线基板1上的整个面上形成抗蚀剂11，对抗蚀剂11进行构图设置跨越多条导体布线4的开口部12。通过进行将导体布线4作为阴极的电解镀Cu，在从开口部12露出的导体布线4上析出镀Cu，如图5E所示形成突起电极5。
图5C～5E沿着经过时间顺序表示将导体布线4作为阴极进行了电解镀Cu的情况下在导体布线4的周围析出镀层的状态，用5a、5b、5表示各个突起电极的形状。
在电解镀Cu工艺中，电镀液中的Cu离子与从作为阴极的导体布线4供给的电子结合，在导体布线4的表面析出镀层。此时，由于在导体布线4的上部消耗Cu离子，在导体布线4的下部电镀液中的Cu离子浓度减少，所以导体布线4的上部的镀层厚度较厚、导体布线4的下部的镀层厚度较薄地析出。因此，即使导体布线4的截面形状是锥形形状，也如图5C～5E所示，在导体布线4的周围析出的突起电极5形成为突起电极5的侧面和导体布线4的背面经由突起电极5的背面以凸形形状平滑地被连接的形状。
接着，如图5F所示，用与突起电极5不同的金属覆盖突起电极5的表面，形成第1导电层6。
接着，如图5G所示，在载物台14上放置布线基板1，利用加热工具13从上面对突起电极5的表面进行加热加压，使导体布线4的背面和突起电极5的背面及侧面的一部分从粘接层3的表面向内部凹陷，使粘接层3熔化，通过第1导电层6与突起电极5粘接。在粘接层3是环氧类的情况下，加热工具13的温度设为200℃～300℃。此时载物台14也进行加热，由此能够在短时间内使粘接层3熔化粘接。
根据此第5实施方式，由于通过将导体布线4作为阴极的电解电镀在导体布线4的周围形成突起电极5，所以，即使导体布线4的截面形状为锥形形状，在导体布线4的周围析出的突起电极5也能够形成为突起电极5的侧面和导体布线4的背面经由突起电极5的背面以凸形形状平滑地被连接的形状。因此，在使突起电极5的背面和侧面的一部分从粘接层3的表面向内部凹陷而与粘接层3粘接时，在突起电极5的侧面和粘接层3之间不产生间隙，而使突起电极5的背面和侧面连续地密接在粘接层3上，可以提高突起电极5和粘接层3的粘接强度。
此外，在突起电极5的表面形成第1导电层6之后，从上面对突起电极5的表面进行加热加压，使突起电极5的背面和侧面的一部分从粘接层3的表面向内部凹陷，通过第1导电层6粘接在粘接层3上，所以，第1导电层6成为势垒，防止突起电极5的材料向粘接层3扩散，能够提高布线基板1的绝缘可靠性。
(第6实施方式)
参照附图，说明本发明的第6实施方式的半导体器件的制造方法。
首先，准备图7A所示的布线基板1。图7A所示的布线基板1与图5F所示的布线基板相同，利用上述第5实施方式的布线基板的制造方法，经过与图5A～图5F相同的工序来制造。
接着，如图7B所示，在载物台14上放置布线基板1，在布线基板1上放置形成有电极焊盘8及覆盖电极焊盘8的表面的第2导电层9的半导体元件7。接着，利用加热工具13从上面对半导体元件7的背面进行加热加压，接合电极焊盘8上的第2导电层9和突起电极5上的第1导电层6的同时，使导体布线4的背面、突起电极5的背面和侧面的一部分从粘接层3的表面向内部凹陷。由此，使粘接层3熔化，通过第1导电层6与突起电极5粘接。
再有，在从半导体芯片的背面进行加热加压的同时施加超声波振幅，由此就能够在短时间内键合第1导电层6和第2导电层9。
根据此第6实施方式，在面朝下地安装半导体元件7的同时，使突起电极5的背面和侧面的一部分从粘接层3的表面向内部凹陷且与粘接层3粘接，由此能够缩短半导体器件的制造时间。

Claims (17)

1、一种布线基板，其特征在于，包括：
绝缘性基材；
粘接层，形成在上述绝缘性基材的表面；
导体布线，形成在上述粘接层的表面；
突起电极，横截上述导体布线的长度方向并遍及上述导体布线两侧的上述粘接层上的区域而形成；
形成有上述突起电极的区域的上述导体布线的背面、和上述突起电极中的在上述导体布线两侧的上述粘接层上形成的区域的背面及侧面的一部分，从上述粘接层的表面向内部凹陷，并与上述粘接层粘接。
2、根据权利要求1所述的布线基板，其特征在于，上述突起电极的宽度比上述导体布线的背面的宽度宽，并且，从上述导体布线的背面经由上述突起电极的背面而到达突起电极侧面的区域的面以凸形形状平滑地被形成。
3、根据权利要求1所述的布线基板，其特征在于，形成在上述绝缘性基材的表面的粘接层的厚度，比形成有上述突起电极的区域的上述导体布线的背面和上述突起电极中的在上述导体布线两侧的上述粘接层上形成的区域的背面及侧面的一部分从上述粘接层的表面向内部凹陷的距离厚。
4、根据权利要求1所述的布线基板，其特征在于，上述突起电极中的上述突起电极的表面及在上述导体布线两侧的上述粘接层上形成的区域，被由不同于上述突起电极的一种以上材质构成的第1导电层覆盖。
5、根据权利要求4所述的布线基板，其特征在于，上述突起电极中的从上述粘接层的表面向内部凹陷的区域的侧面，通过上述第1导电层与上述粘接层粘接。
6、一种布线基板，其特征在于，包括：
绝缘性基材，至少表面具有粘接性；
导体布线，形成在上述绝缘性基材的表面；
突起电极，横截上述导体布线的长度方向并遍及上述导体布线两侧的上述绝缘性基材上的区域而形成，
形成有上述突起电极的区域的上述导体布线的背面、和上述突起电极中的在上述导体布线两侧的上述绝缘性基材上形成的区域的背面及侧面的一部分，从上述绝缘性基材的表面向内部凹陷，并与上述绝缘性基材粘接。
7、根据权利要求6所述的布线基板，其特征在于，横截上述导体布线的长度方向并遍及上述导体布线两侧的上述绝缘性基材上的区域而形成的突起电极的宽度，比上述导体布线的背面的宽度宽；并且，该布线基板具有上述突起电极侧面和上述导体布线的背面经由上述突起电极的背面以凸形形状平滑地连接的形状。
8、根据权利要求6所述的布线基板，其特征在于，上述突起电极中的上述突起电极的表面及在上述导体布线两侧的上述绝缘性基材上形成的区域，被由不同于上述突起电极的一种以上材质构成的第1导电层覆盖。
9、根据权利要求8所述的布线基板，其特征在于，上述突起电极中的从上述绝缘性基材的表面向内部凹陷的区域的侧面，通过上述第1导电层与上述绝缘性基材粘接。
10、一种半导体器件，其特征在于，具备如权利要求1所述的布线基板和在上述布线基板上装载的半导体芯片，上述半导体芯片的电极焊盘与形成在上述布线基板上的突起电极电连接。
11、根据权利要求10所述的半导体器件，其特征在于，在上述电极焊盘的表面具有由与上述电极焊盘不同的一种以上材质构成的第2导电层。
12、一种半导体器件，其特征在于，具备如权利要求6所述的布线基板和在上述布线基板上装载的半导体芯片，上述半导体芯片的电极焊盘与形成在上述布线基板上的突起电极电连接。
13、根据权利要求12所述的半导体器件，其特征在于，在上述电极焊盘表面具有由与上述电极焊盘不同的一种以上材质构成的第2导电层。
14、一种布线基板的制造方法，其特征在于，包括：
准备在绝缘性基材上具有粘接层并在上述粘接层上层叠导体层的层叠基材的工序；
对上述层叠基材的表面的上述导体层进行构图而形成导体布线的工序；
通过将上述导体布线作为阴极的电解电镀，横截上述导体布线的长度方向并遍及上述导体布线两侧的上述粘接层上的区域而形成突起电极的工序；及
从上面对上述突起电极进行加热加压，使上述突起电极之下的上述导体布线的背面和上述突起电极中的在上述导体布线两侧的上述粘接层上形成的区域的背面和侧面的一部分，从上述粘接层的表面向内部凹陷，与上述粘接层粘接的工序。
15、根据权利要求14所述的布线基板的制造方法，其特征在于，通过将上述导体布线作为阴极的电解电镀，横截上述导体布线的长度方向并遍及上述导体布线两侧的上述粘接层上的区域而形成突起电极的工序之后，
包括：将上述突起电极的表面及上述突起电极中的在上述导体布线两侧的上述粘接层上形成的区域，利用由与上述突起电极不同的一种以上材质构成的导电层来覆盖的工序；
从上面对由上述导电层覆盖的突起电极进行加热加压，使上述突起电极中的在上述导体布线两侧的上述粘接层上形成的区域的背面和侧面的一部分，从上述粘接层的表面向内部凹陷，通过上述导电层与上述粘接层粘接。
16、一种半导体器件的制造方法，其特征在于，包括：
准备在绝缘性基材上具有粘接层并在上述粘接层上层叠导体层的层叠基材的工序；
对上述层叠基材的表面的上述导体层进行构图而形成导体布线的工序；
通过将上述导体布线作为阴极的电解电镀，横截上述导体布线的长度方向并遍及上述导体布线两侧的上述粘接层上的区域而形成突起电极的工序；
将上述突起电极的表面及上述突起电极中的在上述导体布线两侧的上述粘接层上形成的区域，利用由与上述突起电极不同的材质形成的导电层来覆盖的工序；
准备在与上述突起电极相对的位置具有电极焊盘的半导体芯片的工序；
使上述半导体芯片的上述电极焊盘和上述突起电极相对放置，从上述半导体芯片的背面进行加热加压而使上述电极焊盘和上述突起电极的表面的导电层加热压接的同时，使上述突起电极中的在上述导体布线两侧的上述粘接层上形成的区域的背面和侧面的一部分从上述粘接层的表面向内部凹陷，通过上述导电层与上述粘接层粘接的工序。
17、根据权利要求16所述的半导体器件的制造方法，其特征在于，与从半导体芯片的背面进行加热加压的工序同时施加超声波振动。
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