JPWO2018159678A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JPWO2018159678A1 JPWO2018159678A1 JP2019503063A JP2019503063A JPWO2018159678A1 JP WO2018159678 A1 JPWO2018159678 A1 JP WO2018159678A1 JP 2019503063 A JP2019503063 A JP 2019503063A JP 2019503063 A JP2019503063 A JP 2019503063A JP WO2018159678 A1 JPWO2018159678 A1 JP WO2018159678A1
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Abstract
Description
図1は、本実施の形態1における半導体装置の断面図である。図2は、本実施の形態1における半導体装置の平面図である。図1に示す半導体装置の断面は、図2の線分A−Aに沿った断面である。なお、図2において、図の見易さのために第2の封止材72およびキャップ6を仮想線で記載している。
本実施の形態1における半導体装置の製造方法を説明する。まず、ベース基板3を用意する。次に、リフロー方式で電子部品5を導電層33に接合する。つまり、ベース基板3の導電層33の導電パターン332,333上に接合材51、即ちソルダペーストを配置し、接合材51に電子部品5を搭載した状態で接合材51を加熱して溶解させる。
本実施の形態1における半導体装置は、絶縁層32と、絶縁層32の一方主面に接合された導電層33と、絶縁層32の前記一方主面と上面が同じ方向を向くように配置された半導体素子1と、を備え、半導体素子1の上面には上面電極9が設けられ、一端が半導体素子1の上面電極9に電気的に接合され、他端が導電層33に電気的に接合された、中空部分4aを有する配線部材4と、第1の封止材71と、第1の封止材71よりも柔らかい第2の封止材72と、をさらに備え、第1の封止材71は、半導体素子1と接触するように半導体素子1の少なくとも一部を封止し、第2の封止材72は、配線部材4と接触するように配線部材4を封止する。
図3は、本実施の形態2における半導体装置の断面図である。図4は、本実施の形態2における半導体装置の平面図である。図3に示す半導体装置の断面は、図4の線分B−Bに沿った断面である。なお、図4において、図の見易さのために第2の封止材72およびキャップ6を仮想線で記載している。
図5から図9は、本実施の形態2における半導体装置の製造工程を示す図である。まず、ベース基板3を用意する。次に、図5に示すように、リフロー方式で電子部品5を導電層33に接合する。つまり、ベース基板3の導電層33の導電パターン332,333上に接合材51、即ちソルダペーストを配置し、接合材51に電子部品5を搭載した状態で接合材51を加熱して溶解させる。
本実施の形態2における半導体装置は、放熱板31をさらに備え、放熱板31の一方主面には絶縁層32の他方主面が接合され、放熱板31の一方主面には、放熱板31が絶縁層32で覆われていない開口部8が設けられ、開口部8において、半導体素子1の下面が放熱板31の一方主面に接合され、第1の封止材71は、半導体素子1の少なくとも一部および開口部8を封止する。
図10は、本実施の形態3における半導体装置の断面図である。図11は、本実施の形態3における半導体装置の平面図である。図10に示す半導体装置の断面は、図11の線分C−Cに沿った断面である。なお、図11において、図の見易さのために第2の封止材72およびキャップ6を仮想線で記載している。
本実施の形態3における半導体装置において、絶縁層32の一方主面の高さ以上まで、開口部8が第1の封止材71で満たされる。これにより、第1の封止材71と絶縁層32の側面32aとの接触面積が増大するため、第1の封止材71と放熱板31との密着性が向上し、半導体装置の信頼性をより向上させることが可能になる。特に、絶縁層32をガラスエポキシとし、第1の封止材71をエポキシ樹脂とした場合。エポキシ樹脂はガラスエポキシと密着性が高いため、第1の封止材71は、開口部8において絶縁層32の側面32aに良好に接着する。そのため、第1の封止材71と放熱板31との密着性がより向上し、半導体装置の信頼性をさらに向上させることが可能になる。
図13は、本実施の形態4における半導体装置の断面図である。図14は、本実施の形態4における半導体装置の平面図である。図13に示す半導体装置の断面は、図14の線分D−Dに沿った断面である。なお、図14において、図の見易さのために第2の封止材72およびキャップ6を仮想線で記載している。
本実施の形態4における半導体装置において、第1の封止材71は、配線部材4の中空部分4aに接触しないように、半導体素子1の少なくとも一部を封止し、第2の封止材72は、配線部材4の中空部分4aの全体と接触する。
図15は、本実施の形態5における半導体装置の平面図である。なお、図15において、図の見易さのために第2の封止材72およびキャップ6を仮想線で記載している。実施の形態2では、ベース基板3の開口部8全体を第1の封止材71で封止した。
本実施の形態5において、半導体素子1は平面視で長方形状であり、第1の封止材71は、半導体素子1の四隅を封止し、第1の封止材71は、平面視で2組の対向する辺のうち、どちらか一方の組の対向する辺に沿って延在する。
図16は、本実施の形態6における半導体装置の平面図である。なお、図16において、図の見易さのために第2の封止材72およびキャップ6を仮想線で記載している。実施の形態5では、半導体素子1の四隅および互いに対向する短辺が第1の封止材71で封止された。一方、本実施の形態6では、半導体素子1の四隅および互いに対向する長辺が第1の封止材71で封止される。本実施の形態6の半導体装置のその他の構成は、実施の形態5の半導体装置と同じため、説明を省略する。
本実施の形態6における半導体装置において、第1の封止材71は、半導体素子1の平面視で2組の対向する辺のうち、辺の長さがより長い組の対向する辺に沿って延在する。本実施の形態6では、互いに対向する短辺に代えて、互いに対向する長辺を第1の封止材71で封止することにより、少ない量の第1の封止材71で、半導体素子1および接合材2をより強固に保持することが可能となる。従って、第1の封止材71の内部にボイドが発生する可能性を低減することと、半導体装置の高い信頼性とを両立することが可能である。
図17は、本実施の形態7における半導体装置の平面図である。図18は、本実施の形態7における半導体装置の断面図である。図18に示す半導体装置の断面は、図17の線分E−Eに沿った断面である。なお、図17において、図の見易さのために第2の封止材72およびキャップ6を仮想線で記載している。また、図19はエアブリッジ存在領域100を模式的に示す平面図である。図19において、第1の封止材71の図示を省略している。
高周波半導体装置に用いられる半導体素子は、平面視して長方形の形状をしていることが多く、正方形の場合と比較して、接合材2を形成するダイボンド処理後に半導体素子1の長手方向に沿って傾きが発生しやすい。そのため、前述したように、半導体素子1の四隅においてもダイボンド層である接合材2の厚みにバラつきが発生する。一般的に、接合材2の膜厚が厚いと応力緩和性が大きく、接合材2の膜厚が薄いと応力緩和性が小さくなる。そのため、半導体素子1の四隅の接合材2の膜厚がバラつくと、四隅における熱衝撃試験などに対する信頼性もバラついてしまい、最も弱い隅から接合材2が劣化し、信頼性としても最も弱い隅に律速してしまう。
前記絶縁層の前記一方主面と上面が同じ方向を向くように配置された半導体素子とを備えた半導体装置であって、前記半導体素子の前記上面には上面電極が設けられ、前記半導体装置は、一端が前記半導体素子の前記上面電極に電気的に接合され、他端が前記導電層に電気的に接合され、中空部分を有する配線部材と、第1の封止材と、第2の封止材と、をさらに備え、前記第1の封止材は、前記半導体素子と接触するように前記半導体素子の少なくとも一部を封止し、前記第2の封止材は、前記配線部材と接触するように前記配線部材を封止し、前記第1の封止材はエポキシ樹脂であり、前記第2の封止材はシリコーンゲルであり、前記半導体装置は、放熱板をさらに備え、前記放熱板の一方主面には前記絶縁層の他方主面が接合され、前記放熱板の前記一方主面には、前記放熱板が前記絶縁層で覆われていない開口部が設けられ、前記開口部において、前記半導体素子の下面が前記放熱板の前記一方主面に接合され、前記第1の封止材は、前記半導体素子の少なくとも一部および前記開口部を封止し、前記第1の封止材は前記配線部材の一端をさらに封止し、前記第2の封止材は前記配線部材の他端をさらに封止する。
Claims (21)
- 絶縁層と、
前記絶縁層の一方主面に接合された導電層と、
前記絶縁層の前記一方主面と上面が同じ方向を向くように配置された半導体素子と、
を備え、
前記半導体素子の前記上面には上面電極が設けられ、
一端が前記半導体素子の前記上面電極に電気的に接合され、他端が前記導電層に電気的に接合され、中空部分を有する配線部材と、
第1の封止材と、
前記第1の封止材よりも柔らかい第2の封止材と、
をさらに備え、
前記第1の封止材は、前記半導体素子と接触するように前記半導体素子の少なくとも一部を封止し、
前記第2の封止材は、前記配線部材と接触するように前記配線部材を封止する、
半導体装置。 - 放熱板をさらに備え、
前記放熱板の一方主面には前記絶縁層の他方主面が接合され、
前記放熱板の前記一方主面には、前記放熱板が前記絶縁層で覆われていない開口部が設けられ、
前記開口部において、前記半導体素子の下面が前記放熱板の前記一方主面に接合され、
前記第1の封止材は、前記半導体素子の少なくとも一部および前記開口部を封止する、
請求項1に記載の半導体装置。 - 前記絶縁層の前記一方主面の高さ以上まで、前記開口部が前記第1の封止材で満たされる、
請求項2に記載の半導体装置。 - 前記開口部において、前記絶縁層の前記一方主面は前記半導体素子の前記上面よりも高く配置される、
請求項3に記載の半導体装置。 - 前記第1の封止材は、前記配線部材の前記中空部分に接触しないように、前記半導体素子の少なくとも一部を封止し、
前記第2の封止材は、前記配線部材の前記中空部分の全体と接触する、
請求項1から請求項4のいずれか一項に記載の半導体装置。 - 前記配線部材の前記第1の封止材に接触している面積よりも、前記配線部材の前記第2の封止材に接触している面積の方が大きい、
請求項1から請求項4のいずれか一項に記載の半導体装置。 - 前記第1の封止材は、前記半導体素子の前記上面と接触しないように、前記半導体素子の一部を封止する、
請求項1から請求項4のいずれか一項に記載の半導体装置。 - 前記配線部材はワイヤである、
請求項1から請求項7のいずれか一項に記載の半導体装置。 - 前記第2の封止材の曲げ弾性率は、前記第1の封止材の曲げ弾性率よりも小さい、
請求項1から請求項8のいずれか一項に記載の半導体装置。 - 前記絶縁層はガラスエポキシであり、
前記第1の封止材はエポキシ樹脂である、
請求項1から請求項9のいずれか一項に記載の半導体装置。 - 前記第1の封止材はエポキシ樹脂であり、
前記第2の封止材はシリコーンゲルである、
請求項1から請求項10のいずれか一項に記載の半導体装置。 - 前記半導体素子と前記放熱板とを接合する接合材は導電性樹脂であり、
前記導電性樹脂は、
エポキシ樹脂、アクリル樹脂、シリコーンのいずれかと、
金属フィラーと、
を含む、
請求項2から請求項4のいずれか一項に記載の半導体装置。 - 前記半導体素子と前記放熱板とを接合する接合材は、焼結性接合材である、
請求項2から請求項4のいずれか一項に記載の半導体装置。 - 前記半導体素子と前記放熱板とを接合する接合材の表面は多孔質状である、
請求項2から請求項4のいずれか一項に記載の半導体装置。 - 前記半導体素子は平面視で長方形状であり、
前記第1の封止材は、前記半導体素子の四隅を封止し、
前記第1の封止材は、前記半導体素子の四隅それぞれで離散して存在する、
請求項1から請求項14のいずれか一項に記載の半導体装置。 - 前記半導体素子と前記放熱板とを接合する接合材をさらに備え、
前記半導体素子は平面視で長方形状であり、
前記第1の封止材は、前記半導体素子の四隅を封止しており、
前記接合材は、前記半導体素子の平面視で2組の対向する辺のうち、辺の長さがより短い組の対向する一方の辺側の膜厚が、他方の辺側の膜厚より薄くなるように設けられ、
前記第1の封止材は、前記一方の辺側における二隅の形成量が、前記他方の辺側における二隅の形成量よりも大きくなるように設けられる、
請求項2から請求項4のいずれか一項に記載の半導体装置。 - 前記半導体素子は平面視で長方形状であり、
前記第1の封止材は、前記半導体素子の四隅を封止し、
前記第1の封止材は、前記半導体素子の平面視で2組の対向する辺のうち、どちらか一方の組の対向する辺に沿って延在する、
請求項1から請求項14のいずれか一項に記載の半導体装置。 - 前記第1の封止材は、前記半導体素子の平面視で2組の対向する辺のうち、辺の長さがより短い組の対向する辺に沿って延在する、
請求項17に記載の半導体装置。 - 前記第1の封止材は、前記半導体素子の平面視で2組の対向する辺のうち、辺の長さがより長い組の対向する辺に沿って延在する、
請求項17に記載の半導体装置。 - 前記半導体素子は高周波信号の増幅又はスイッチングを行う素子である、
請求項1から請求項19のいずれか一項に記載の半導体装置。 - 前記半導体素子はワイドバンドギャップ半導体を材料とする、
請求項20に記載の半導体装置。
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US11387210B2 (en) | 2019-03-15 | 2022-07-12 | Fuji Electric Co., Ltd. | Semiconductor module and manufacturing method therefor |
WO2020230457A1 (ja) * | 2019-05-16 | 2020-11-19 | Ngkエレクトロデバイス株式会社 | パワー半導体モジュールおよびその製造方法 |
US11728238B2 (en) * | 2019-07-29 | 2023-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package with heat dissipation films and manufacturing method thereof |
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JPS5910245A (ja) | 1982-07-09 | 1984-01-19 | Hitachi Ltd | 樹脂封止半導体装置とその製造法 |
US5012323A (en) * | 1989-11-20 | 1991-04-30 | Micron Technology, Inc. | Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe |
JPH0582678A (ja) * | 1991-09-24 | 1993-04-02 | Sanyo Electric Co Ltd | 混成集積回路 |
US5831836A (en) * | 1992-01-30 | 1998-11-03 | Lsi Logic | Power plane for semiconductor device |
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JP3196821B2 (ja) | 1997-01-16 | 2001-08-06 | サンケン電気株式会社 | 樹脂封止型回路装置 |
JP2000332160A (ja) | 1999-05-24 | 2000-11-30 | Sumitomo Metal Electronics Devices Inc | キャビティダウン型半導体パッケージ |
JP2001267340A (ja) | 2000-03-16 | 2001-09-28 | Hitachi Ltd | 半導体装置の製造方法 |
JP4492448B2 (ja) | 2005-06-15 | 2010-06-30 | 株式会社日立製作所 | 半導体パワーモジュール |
JP5023792B2 (ja) * | 2007-04-26 | 2012-09-12 | 株式会社デンソー | 半導体圧力センサ装置 |
US8354688B2 (en) * | 2008-03-25 | 2013-01-15 | Bridge Semiconductor Corporation | Semiconductor chip assembly with bump/base/ledge heat spreader, dual adhesives and cavity in bump |
WO2012144070A1 (ja) * | 2011-04-22 | 2012-10-26 | 三菱電機株式会社 | 半導体装置 |
JP2013008720A (ja) * | 2011-06-22 | 2013-01-10 | Panasonic Corp | 電子デバイスの製造方法 |
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JP6791621B2 (ja) * | 2015-09-11 | 2020-11-25 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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