JPWO2016181710A1 - 薄膜デバイス - Google Patents
薄膜デバイス Download PDFInfo
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- JPWO2016181710A1 JPWO2016181710A1 JP2017515872A JP2017515872A JPWO2016181710A1 JP WO2016181710 A1 JPWO2016181710 A1 JP WO2016181710A1 JP 2017515872 A JP2017515872 A JP 2017515872A JP 2017515872 A JP2017515872 A JP 2017515872A JP WO2016181710 A1 JPWO2016181710 A1 JP WO2016181710A1
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- thin film
- resin layer
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- 239000010409 thin film Substances 0.000 title claims abstract description 378
- 239000011347 resin Substances 0.000 claims abstract description 108
- 229920005989 resin Polymers 0.000 claims abstract description 108
- 239000002184 metal Substances 0.000 claims abstract description 74
- 229910052751 metal Inorganic materials 0.000 claims abstract description 74
- 230000003014 reinforcing effect Effects 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 25
- 239000003990 capacitor Substances 0.000 claims description 39
- 238000005452 bending Methods 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 106
- 238000000605 extraction Methods 0.000 description 25
- 239000010408 film Substances 0.000 description 25
- 239000000463 material Substances 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 10
- 238000000206 photolithography Methods 0.000 description 9
- 239000011241 protective layer Substances 0.000 description 9
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 7
- 238000007740 vapor deposition Methods 0.000 description 7
- 229910052804 chromium Inorganic materials 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000000203 mixture Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 230000002457 bidirectional effect Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000002787 reinforcement Effects 0.000 description 2
- 229910019974 CrSi Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Ceramic Capacitors (AREA)
Abstract
Description
本発明の第1実施形態について図1〜図3を参照して説明する。なお、図1および図2では、説明を簡易なものとするために本発明にかかる主要な構成のみが図示されている。また、後の説明で参照する図4および図5についても、図1および図2と同様に主要な構成のみが図示されているが、以下の説明においてはその説明は省略する。
薄膜デバイス100の概略構成について説明する。
薄膜デバイス100の製造方法の一例について説明する。なお、この実施形態では、大面積の基板1が用いられて複数の薄膜デバイス100の集合体が形成された後に個片化されることにより、複数の薄膜デバイス100が同時に形成される。なお、以下の説明においては、ESD保護素子D1,D2の形成方法の説明は省略する。
本発明の第2の実施形態について図4を参照して説明する。
薄膜デバイス100aの概略構成について説明する。
薄膜デバイス100aの製造方法の一例について説明する。なお、上記した第1実施形態と同様に、大面積の基板1が用いられて複数の薄膜デバイス100aの集合体が形成された後に個片化されることにより、複数の薄膜デバイス100aが同時に形成される。
本発明の第3の実施形態について図5を参照して説明する。
2,3,4 樹脂層
1a,2a,3a,4a 一方主面
11a,11b 第2の金属薄膜
12 抵抗薄膜
12a 第1の補強用薄膜
12b 第2の補強用薄膜
12c,12d 接続電極
15a〜15c 第1の金属薄膜
100,100a 薄膜デバイス
C 薄膜キャパシタ素子
D1,D2 ESD保護素子
P1 第1外部電極
P2 第2外部電極
P3 第3外部電極
P4 第4外部電極
R 薄膜抵抗素子
R1 第1の薄膜抵抗素子(薄膜抵抗素子)
R2 第2の薄膜抵抗素子(薄膜抵抗素子)
W1,W2 電流パス
Claims (7)
- 基板と、
前記基板の一方主面側に積層された複数の樹脂層とを備え、
前記複数の樹脂層は、
薄膜抵抗素子が一方主面に設けられた第1の樹脂層と、
前記第1の樹脂層の前記基板と反対側に配置された第1の金属薄膜が一方主面に設けられた第2の樹脂層とを含み、
前記薄膜抵抗素子は、
抵抗薄膜と、前記抵抗薄膜上に形成された第1の補強用薄膜とを有し、
前記第1の補強用薄膜が、前記第1の金属薄膜と平面視で重ならない部分に配置されている
ことを特徴とする薄膜デバイス。 - 前記薄膜抵抗素子は、
前記抵抗薄膜上に形成された接続電極をさらに有し、
前記第1の補強用薄膜と前記接続電極とが同一のプロセスにより同時に形成されていることを特徴とする請求項1に記載の薄膜デバイス。 - 前記抵抗薄膜は、Siを含有することを特徴とする請求項1または2に記載の薄膜デバイス。
- 前記抵抗薄膜の抵抗率が、前記第1の補強用薄膜の抵抗率よりも大きいことを特徴とする請求項1ないし3のいずれかに記載の薄膜デバイス。
- 前記複数の樹脂層は、
前記第1の樹脂層の前記基板側に配置された第2の金属薄膜が一方主面に設けられた第3の樹脂層をさらに含み、
前記薄膜抵抗素子は、
前記抵抗薄膜上に形成された第2の補強用薄膜をさらに有し、
前記第2の補強用薄膜が、前記第2の金属薄膜と平面視で重ならない部分に配置されている
ことを特徴とする請求項1ないし4のいずれかに記載の薄膜デバイス。 - 第1〜第4外部電極と、
前記第1、第2外部電極間に直列接続された可変容量型の薄膜キャパシタ素子と、
一端が前記第3外部電極に接続された第1の前記薄膜抵抗素子と、
一端が前記第4外部電極に接続された第2の前記薄膜抵抗素子とを備え、
前記第1、第2の薄膜抵抗素子の他端間に前記薄膜キャパシタ素子が挿入されるように、前記第1、第2の薄膜抵抗素子それぞれの他端が前記薄膜キャパシタ素子両端のそれぞれに接続されていることを特徴とする請求項1ないし5いずれかに記載の薄膜デバイス。 - 所定電圧以上の静電気放電が生じた場合に前記第1、第2の薄膜抵抗素子および前記薄膜キャパシタ素子を経由しない電流パスを形成するESD保護素子をさらに備えることを特徴とする請求項6に記載の薄膜デバイス。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015098307 | 2015-05-13 | ||
JP2015098307 | 2015-05-13 | ||
PCT/JP2016/059103 WO2016181710A1 (ja) | 2015-05-13 | 2016-03-23 | 薄膜デバイス |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2016181710A1 true JPWO2016181710A1 (ja) | 2017-08-10 |
JP6191804B2 JP6191804B2 (ja) | 2017-09-06 |
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Family Applications (1)
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JP2017515872A Active JP6191804B2 (ja) | 2015-05-13 | 2016-03-23 | 薄膜デバイス |
Country Status (3)
Country | Link |
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JP (1) | JP6191804B2 (ja) |
CN (1) | CN207572353U (ja) |
WO (1) | WO2016181710A1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6562161B2 (ja) | 2017-02-17 | 2019-08-21 | 株式会社村田製作所 | 薄膜デバイスおよび薄膜デバイスの製造方法 |
DE112021006302T5 (de) * | 2021-01-08 | 2023-09-21 | Rohm Co., Ltd. | Elektronische komponente |
WO2023112551A1 (ja) * | 2021-12-17 | 2023-06-22 | ローム株式会社 | 半導体装置およびその製造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03225950A (ja) * | 1990-01-31 | 1991-10-04 | Sony Corp | 半導体装置の製造方法 |
US20060228879A1 (en) * | 2005-04-08 | 2006-10-12 | Texas Instruments Incorporated | Thin film resistor head structure and method for reducing head resistivity variance |
JP2006332428A (ja) * | 2005-05-27 | 2006-12-07 | Seiko Instruments Inc | 半導体集積回路装置 |
JP2015088585A (ja) * | 2013-10-30 | 2015-05-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
-
2016
- 2016-03-23 WO PCT/JP2016/059103 patent/WO2016181710A1/ja active Application Filing
- 2016-03-23 JP JP2017515872A patent/JP6191804B2/ja active Active
- 2016-03-23 CN CN201690000755.4U patent/CN207572353U/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03225950A (ja) * | 1990-01-31 | 1991-10-04 | Sony Corp | 半導体装置の製造方法 |
US20060228879A1 (en) * | 2005-04-08 | 2006-10-12 | Texas Instruments Incorporated | Thin film resistor head structure and method for reducing head resistivity variance |
JP2006332428A (ja) * | 2005-05-27 | 2006-12-07 | Seiko Instruments Inc | 半導体集積回路装置 |
JP2015088585A (ja) * | 2013-10-30 | 2015-05-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Also Published As
Publication number | Publication date |
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CN207572353U (zh) | 2018-07-03 |
JP6191804B2 (ja) | 2017-09-06 |
WO2016181710A1 (ja) | 2016-11-17 |
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