JP6319467B2 - 薄膜デバイス - Google Patents
薄膜デバイス Download PDFInfo
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- JP6319467B2 JP6319467B2 JP2016574686A JP2016574686A JP6319467B2 JP 6319467 B2 JP6319467 B2 JP 6319467B2 JP 2016574686 A JP2016574686 A JP 2016574686A JP 2016574686 A JP2016574686 A JP 2016574686A JP 6319467 B2 JP6319467 B2 JP 6319467B2
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- 239000010409 thin film Substances 0.000 title claims description 336
- 239000011347 resin Substances 0.000 claims description 109
- 229920005989 resin Polymers 0.000 claims description 109
- 239000000758 substrate Substances 0.000 claims description 41
- 239000003990 capacitor Substances 0.000 claims description 38
- 238000000034 method Methods 0.000 claims description 24
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 230000000452 restraining effect Effects 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 111
- 238000000605 extraction Methods 0.000 description 32
- 239000010408 film Substances 0.000 description 24
- 238000000206 photolithography Methods 0.000 description 9
- 238000005452 bending Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000011241 protective layer Substances 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 229910052804 chromium Inorganic materials 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229920002577 polybenzoxazole Polymers 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910019974 CrSi Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5228—Resistive arrangements or effects of, or between, wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Non-Adjustable Resistors (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Description
本発明の第1実施形態について図1〜図3を参照して説明する。なお、図1および図2では、説明を簡易なものとするために本発明にかかる主要な構成のみが図示されている。また、後の説明で参照する図4〜図6についても、図1および図2と同様に主要な構成のみが図示されているが、以下の説明においてはその説明は省略する。
薄膜デバイス100の概略構成について説明する。
薄膜デバイス100の製造方法の一例について説明する。なお、この実施形態では、大面積の基板1が用いられて複数の薄膜デバイス100の集合体が形成された後に個片化されることにより、複数の薄膜デバイス100が同時に形成される。なお、以下の説明においては、ESD保護素子D1,D2の形成方法の説明は省略する。
本発明の第2の実施形態について図4および図5を参照して説明する。
本発明の第3の実施形態について図6を参照して説明する。
薄膜デバイス100aの概略構成について説明する。
薄膜デバイス100aの製造方法の一例について説明する。なお、上記した第1実施形態と同様に、大面積の基板1が用いられて複数の薄膜デバイス100aの集合体が形成された後に個片化されることにより、複数の薄膜デバイス100aが同時に形成される。
2,3,4 樹脂層
1a,2a,3a,4a 一方主面
11 第2の拘束用薄膜
13 引出電極(配線用薄膜電極)
14 第1の拘束用薄膜
100,100a 薄膜デバイス
C 薄膜キャパシタ素子
D1,D2 ESD保護素子
P1 第1外部電極
P2 第2外部電極
P3 第3外部電極
P4 第4外部電極
R 薄膜抵抗素子
R1 第1の薄膜抵抗素子(薄膜抵抗素子)
R2 第2の薄膜抵抗素子(薄膜抵抗素子)
W1,W2 電流パス
Claims (9)
- 基板と、
前記基板の一方主面側に積層された複数の樹脂層と、を備え、
前記複数の樹脂層は、
薄膜形成プロセスによって形成された薄膜抵抗素子が一方主面に設けられた第1の樹脂層と、
前記第1の樹脂層の前記基板と反対側に配置され、薄膜形成プロセスにより形成された第1の拘束用薄膜が一方主面に設けられた第2の樹脂層とを含み、
前記薄膜抵抗素子と前記第1の拘束用薄膜とが平面視で重なるように配置されており、
前記薄膜抵抗素子は、その一端部から他端部までの全体が、平面視で前記第1の拘束用薄膜と重なる、
ことを特徴とする薄膜デバイス。 - 前記薄膜抵抗素子は、複数の薄膜抵抗素子であり、
前記複数の薄膜抵抗素子の全ては、その一端部から他端部までの全体が、平面視で前記第1の拘束用薄膜と重なる、
ことを特徴とする請求項1に記載の薄膜デバイス。 - 前記第2の樹脂層の一方主面に、薄膜形成プロセスにより形成されて前記薄膜抵抗素子に電気的に接続された配線用薄膜電極が形成されている、ことを特徴とする請求項1または2に記載の薄膜デバイス。
- 前記第1の拘束用薄膜と前記配線用薄膜電極とが分離して形成されている、ことを特徴とする請求項3に記載の薄膜デバイス。
- 前記第1の拘束用薄膜と前記配線用薄膜電極とが一体形成されている、ことを特徴とする請求項3に記載の薄膜デバイス。
- 前記複数の樹脂層は、
前記第1の樹脂層の前記基板側に配置され、薄膜形成プロセスにより形成された第2の拘束用薄膜が一方主面に設けられた第3の樹脂層をさらに含み、
前記薄膜抵抗素子と前記第2の拘束用薄膜とが平面視で重なるように配置されている、
ことを特徴とする請求項1ないし5のいずれか1項に記載の薄膜デバイス。 - 前記薄膜抵抗素子は、Siを含有する、ことを特徴とする請求項1ないし6のいずれか1項に記載の薄膜デバイス。
- 第1〜第4外部電極と、
前記第1、第2外部電極間に直列接続された可変容量型の薄膜キャパシタ素子と、
一端が前記第3外部電極に接続された第1の前記薄膜抵抗素子と、
一端が前記第4外部電極に接続された第2の前記薄膜抵抗素子と、を備え、
前記第1、第2の薄膜抵抗素子の他端間に前記薄膜キャパシタ素子が挿入されるように、前記第1、第2の薄膜抵抗素子それぞれの他端が前記薄膜キャパシタ素子両端のそれぞれに接続されている、
ことを特徴とする請求項1ないし7いずれか1項に記載の薄膜デバイス。 - 所定電圧以上の静電気放電が生じた場合に前記第1、第2の薄膜抵抗素子および前記薄膜キャパシタ素子を経由しない電流パスを形成するESD保護素子をさらに備える、ことを特徴とする請求項8に記載の薄膜デバイス。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015024914 | 2015-02-12 | ||
JP2015024914 | 2015-02-12 | ||
PCT/JP2016/050477 WO2016129304A1 (ja) | 2015-02-12 | 2016-01-08 | 薄膜デバイス |
Publications (2)
Publication Number | Publication Date |
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JPWO2016129304A1 JPWO2016129304A1 (ja) | 2017-09-21 |
JP6319467B2 true JP6319467B2 (ja) | 2018-05-09 |
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JP2016574686A Active JP6319467B2 (ja) | 2015-02-12 | 2016-01-08 | 薄膜デバイス |
Country Status (4)
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US (1) | US10332872B2 (ja) |
JP (1) | JP6319467B2 (ja) |
CN (1) | CN207425835U (ja) |
WO (1) | WO2016129304A1 (ja) |
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US20190304905A1 (en) * | 2018-03-28 | 2019-10-03 | Qualcomm Incorporated | Co-placement of resistor and other devices to improve area & performance |
JP7180359B2 (ja) * | 2018-12-19 | 2022-11-30 | 富士電機株式会社 | 抵抗素子 |
JP7318279B2 (ja) * | 2019-04-03 | 2023-08-01 | 株式会社村田製作所 | キャパシタ |
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US5801065A (en) * | 1994-02-03 | 1998-09-01 | Universal Semiconductor, Inc. | Structure and fabrication of semiconductor device having merged resistive/capacitive plate and/or surface layer that provides ESD protection |
JP2003243522A (ja) * | 2002-02-20 | 2003-08-29 | Mitsubishi Electric Corp | 抵抗素子を使用した半導体装置 |
EP1832619A4 (en) * | 2004-12-28 | 2009-04-29 | Sumitomo Bakelite Co | BENZOXAZOL RESIN, POLYBENZOXAZOLE RESIN, RESIN FILM AND SEMICONDUCTOR DEVICE |
JP2006332428A (ja) * | 2005-05-27 | 2006-12-07 | Seiko Instruments Inc | 半導体集積回路装置 |
JP2009266964A (ja) | 2008-04-23 | 2009-11-12 | Fujikura Ltd | 半導体装置 |
JP5539624B2 (ja) | 2008-04-28 | 2014-07-02 | ラピスセミコンダクタ株式会社 | 薄膜抵抗素子、及び薄膜抵抗素子の製造方法 |
JP5589283B2 (ja) * | 2009-01-30 | 2014-09-17 | 日本電気株式会社 | 配線基板及びその製造方法 |
GB2511233B (en) | 2011-10-26 | 2015-06-24 | Murata Manufacturing Co | Variable capacitance element for wireless communication systems |
CN204442303U (zh) * | 2012-06-08 | 2015-07-01 | 株式会社村田制作所 | 可变电容元件、高频设备以及通信装置 |
JP6091855B2 (ja) * | 2012-11-16 | 2017-03-08 | 太陽誘電株式会社 | 可変容量複合部品 |
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- 2016-01-08 JP JP2016574686A patent/JP6319467B2/ja active Active
- 2016-01-08 CN CN201690000491.2U patent/CN207425835U/zh active Active
- 2016-01-08 WO PCT/JP2016/050477 patent/WO2016129304A1/ja active Application Filing
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Also Published As
Publication number | Publication date |
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WO2016129304A1 (ja) | 2016-08-18 |
CN207425835U (zh) | 2018-05-29 |
JPWO2016129304A1 (ja) | 2017-09-21 |
US10332872B2 (en) | 2019-06-25 |
US20170345815A1 (en) | 2017-11-30 |
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