JPWO2016167283A1 - シンセサイザ - Google Patents
シンセサイザ Download PDFInfo
- Publication number
- JPWO2016167283A1 JPWO2016167283A1 JP2017512558A JP2017512558A JPWO2016167283A1 JP WO2016167283 A1 JPWO2016167283 A1 JP WO2016167283A1 JP 2017512558 A JP2017512558 A JP 2017512558A JP 2017512558 A JP2017512558 A JP 2017512558A JP WO2016167283 A1 JPWO2016167283 A1 JP WO2016167283A1
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- Prior art keywords
- synthesizer
- frequency
- divider
- fine adjustment
- adjustment synthesizer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000010586 diagram Methods 0.000 description 8
- 238000005259 measurement Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 6
- 230000010355 oscillation Effects 0.000 description 6
- 238000001228 spectrum Methods 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 3
- 230000001629 suppression Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
- H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/185—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using a mixer in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
Claims (7)
- 粗調整用シンセサイザおよび微調整用シンセサイザを備えたシンセサイザであって、
前記粗調整用シンセサイザは、リファレンス整数分周器、位相比較器、ループフィルタ、周波数可変発振器、バンドパスフィルタおよび帰還路プログラマブル整数分周器を有する整数型フェーズロックループで構成され、
前記微調整用シンセサイザは、リファレンス整数分周器、位相比較器、ループフィルタ、周波数可変発振器、ミクサ、バンドパスフィルタおよび帰還路プログラマブル小数点分周器を有するフラクショナルフェーズロックループで構成され、
基準信号源の出力が前記粗調整用シンセサイザおよび前記微調整用シンセサイザの双方に並行して入力され、
前記フラクショナルフェーズロックループを構成する前記ミクサには、前記微調整用シンセサイザにおける周波数可変発振器の出力と前記粗微調整用シンセサイザにおける周波数可変発振器の出力とが導かれ、
前記微調整用シンセサイザの出力信号が出力端に導かれ、
前記粗調整用シンセサイザの位相比較周波数を、前記微調整用シンセサイザの位相比較周波数の1/2のべき乗とした
ことを特徴とするシンセサイザ。 - 前記帰還路プログラマブル小数点分周器は、整数分周値および小数分周値で分周数を設定可能であり、
前記小数分周値を0.5とした周波数を中心に、周波数可変帯域幅を位相比較周波数の1/2以下としたことを特徴とする請求項1に記載のシンセサイザ。 - 前記ミクサで周波数変換された際に発生する和周波数の信号および差周波数の信号のうち、前記差周波数の信号を前記帰還路プログラマブル小数点分周器に入力することを特徴とする請求項1に記載のシンセサイザ。
- 前記粗調整用シンセサイザにおける前記帰還路プログラマブル整数分周器の分周数よりも、前記微調整用シンセサイザにおける前記帰還路プログラマブル小数点分周器の分周数を小さくしたことを特徴とする請求項1に記載のシンセサイザ。
- 前記粗調整用シンセサイザの位相比較周波数を前記微調整用シンセサイザの位相比較周波数の1/2に設定すると共に、前記粗調整用シンセサイザにおける前記リファレンス整数分周器の分周数を2に設定することで、前記微調整用シンセサイザにおける前記リファレンス整数分周器を削除したことを特徴とする請求項1に記載のシンセサイザ。
- 前記粗調整用シンセサイザまたは前記微調整用シンセサイザのうちの少なくとも一方を複数のフェーズロックループで構成したことを特徴とする請求項1に記載のシンセサイザ。
- 前記微調整用シンセサイザを構成する前記ミクサを除いて、前記粗調整用シンセサイザと前記微調整用シンセサイザの配置を入れ替え、前記粗調整用シンセサイザに前記ミクサを配置し、前記粗調整用シンセサイザの出力信号が前記出力端に導かれるように構成したことを特徴とする請求項1に記載のシンセサイザ。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015083451 | 2015-04-15 | ||
JP2015083451 | 2015-04-15 | ||
PCT/JP2016/061902 WO2016167283A1 (ja) | 2015-04-15 | 2016-04-13 | シンセサイザ |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2016167283A1 true JPWO2016167283A1 (ja) | 2017-07-27 |
JP6463467B2 JP6463467B2 (ja) | 2019-02-06 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017512558A Active JP6463467B2 (ja) | 2015-04-15 | 2016-04-13 | シンセサイザ |
Country Status (6)
Country | Link |
---|---|
US (1) | US10277235B2 (ja) |
EP (1) | EP3276832B1 (ja) |
JP (1) | JP6463467B2 (ja) |
ES (1) | ES2719545T3 (ja) |
TR (1) | TR201904854T4 (ja) |
WO (1) | WO2016167283A1 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107342765B (zh) * | 2017-08-16 | 2020-06-19 | 吉林大学 | 一种具有灵活可调分频数功能数字分频器的设计 |
CN107769777B (zh) * | 2017-09-27 | 2021-09-24 | 凌阳成芯科技(成都)有限公司 | 一种除数可选的除频器及其除频方法 |
EP3477864B1 (en) * | 2017-10-31 | 2020-07-08 | Nxp B.V. | Apparatus comprising a phase-locked loop |
US20200195262A1 (en) * | 2018-12-12 | 2020-06-18 | Industrial Technology Research Institute | Frequency synthesizer and method thereof |
Citations (5)
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JPH06188733A (ja) * | 1992-12-21 | 1994-07-08 | Toshiba Corp | 周波数シンセサイザ |
JPH11205137A (ja) * | 1998-01-14 | 1999-07-30 | Matsushita Electric Ind Co Ltd | Pll周波数シンセサイザ回路 |
JP2005026891A (ja) * | 2003-06-30 | 2005-01-27 | Sharp Corp | 周波数シンセサイザ、チューナおよび受信機 |
JP2007134832A (ja) * | 2005-11-08 | 2007-05-31 | Nippon Hoso Kyokai <Nhk> | Pll周波数シンセサイザ |
JP2012518336A (ja) * | 2009-02-13 | 2012-08-09 | クゥアルコム・インコーポレイテッド | 複数の同調ループを有する周波数シンセサイザ |
Family Cites Families (24)
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JPH1155113A (ja) | 1997-07-30 | 1999-02-26 | Nippon Telegr & Teleph Corp <Ntt> | 位相同期ループ回路 |
EP0903860A1 (en) * | 1997-09-17 | 1999-03-24 | Matsushita Electric Industrial Co., Ltd. | PLL frequency synthesizer |
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-
2016
- 2016-04-13 ES ES16780074T patent/ES2719545T3/es active Active
- 2016-04-13 JP JP2017512558A patent/JP6463467B2/ja active Active
- 2016-04-13 TR TR2019/04854T patent/TR201904854T4/tr unknown
- 2016-04-13 US US15/552,125 patent/US10277235B2/en active Active
- 2016-04-13 WO PCT/JP2016/061902 patent/WO2016167283A1/ja active Application Filing
- 2016-04-13 EP EP16780074.7A patent/EP3276832B1/en active Active
Patent Citations (5)
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JPH06188733A (ja) * | 1992-12-21 | 1994-07-08 | Toshiba Corp | 周波数シンセサイザ |
JPH11205137A (ja) * | 1998-01-14 | 1999-07-30 | Matsushita Electric Ind Co Ltd | Pll周波数シンセサイザ回路 |
JP2005026891A (ja) * | 2003-06-30 | 2005-01-27 | Sharp Corp | 周波数シンセサイザ、チューナおよび受信機 |
JP2007134832A (ja) * | 2005-11-08 | 2007-05-31 | Nippon Hoso Kyokai <Nhk> | Pll周波数シンセサイザ |
JP2012518336A (ja) * | 2009-02-13 | 2012-08-09 | クゥアルコム・インコーポレイテッド | 複数の同調ループを有する周波数シンセサイザ |
Also Published As
Publication number | Publication date |
---|---|
EP3276832A4 (en) | 2018-04-04 |
US20180048323A1 (en) | 2018-02-15 |
EP3276832A1 (en) | 2018-01-31 |
TR201904854T4 (tr) | 2019-04-22 |
US10277235B2 (en) | 2019-04-30 |
WO2016167283A1 (ja) | 2016-10-20 |
EP3276832B1 (en) | 2019-03-13 |
JP6463467B2 (ja) | 2019-02-06 |
ES2719545T3 (es) | 2019-07-11 |
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