JPWO2016084700A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JPWO2016084700A1 JPWO2016084700A1 JP2016561537A JP2016561537A JPWO2016084700A1 JP WO2016084700 A1 JPWO2016084700 A1 JP WO2016084700A1 JP 2016561537 A JP2016561537 A JP 2016561537A JP 2016561537 A JP2016561537 A JP 2016561537A JP WO2016084700 A1 JPWO2016084700 A1 JP WO2016084700A1
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- oxide film
- insulating layer
- drain electrode
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Abstract
Description
以下、図面を参照しながら、本発明による半導体装置の第1の実施形態を説明する。本実施形態の半導体装置は、酸化物半導体TFTを備えている。なお、本実施形態の半導体装置は、酸化物半導体TFTを備えていればよく、アクティブマトリクス基板、各種表示装置、電子機器などを広く含む。
以下、図面を参照しながら、半導体装置100Bの製造方法を例に、本実施形態の半導体装置の製造方法の一例を説明する。
本発明者は、キレート洗浄の有無とコンタクト抵抗との関係について検討したので、その方法および結果を説明する。
半導体装置100A、100Bの製造プロセスでは、マスクの位置合わせのために、基板上にアライメントマークを設けてもよい。アライメントマークは、例えばソース・ドレイン電極7と同一の導電膜(ソース配線層)を用いて形成される。アライメントマークの読み取りは、例えば、光を照射したときの反射率によって行われる。
半導体装置100A、100Bでは、ソース・ドレイン電極7を含む配線層(ソース配線層と呼ぶ。)が、上述した積層構造を有していてもよい。ソース配線層の表面(上面および側面)は、Cu酸化膜8で覆われていてもよい。ソース配線層のうち他の導電層とコンタクトを形成する部分(例えば端子部など)では、上述したドレイン電極7D−透明導電層19間のコンタクト部と同様に、Cu酸化膜8が除去されていることが好ましい。これにより、コンタクト抵抗の上昇を抑制できる。
以下、本発明による半導体装置の第2の実施形態を説明する。本実施形態の半導体装置は、ソースおよびドレイン電極の表面にCu合金酸化膜が形成されている点で、第1の実施形態と異なっている。
次いで、本実施形態の半導体装置の製造方法を、半導体装置200Bの製造方法を例に説明する。なお、半導体装置200Bにおける各層の材料、厚さおよび形成方法については、半導体装置100A、100Bにおける各層の材料、厚さおよび形成方法と同様の場合には説明を省略する。
以下、図面を参照しながら、本実施形態の他の半導体装置を説明する。
半導体装置200A〜200Cの製造プロセスでは、マスクの位置合わせのために、基板1上にアライメントマークを設けてもよい。アライメントマークは、例えばソース・ドレイン電極7と同一の導電膜(ソース配線層)を用いて形成される。アライメントマークの読み取りは、例えば、光を照射したときの反射率によって行われる。
半導体装置200A〜200Cは、ソース・ドレイン電極7を含む配線層(ソース配線層と呼ぶ。)が、上述した積層構造を有していてもよい。ソース配線層の表面(上面および側面)は、Cu合金酸化膜10で覆われていてもよい。ソース配線層のうち他の導電層とコンタクトを形成するコンタクト部(「追加のコンタクト部」ともいう。)では、上述したドレイン電極7D−透明導電層19間のコンタクト部と同様に、Cu合金酸化膜10が除去されていることが好ましい。これにより、コンタクト抵抗の上昇を抑制できる。追加のコンタクト部は、例えば、ソース端子部、ゲート端子部またはソース−ゲート接続層であってもよい。これらの構成は、前述の実施形態と同様である。
以下、図面を参照しながら、本発明による半導体装置の第3の実施形態を説明する。
3 ゲート電極
4 ゲート絶縁層
5 酸化物半導体層(活性層)
5s ソースコンタクト領域
5d ドレインコンタクト領域
5c チャネル領域
7S ソース電極
7D ドレイン電極
7a 主層
7U 上層
7L 下層
8 Cu酸化膜
9 金属酸化膜
10 Cu合金酸化膜
11 層間絶縁層
12 第1絶縁層
13 第2絶縁層
15 共通電極
17 第3絶縁層
19 透明導電層(画素電極)
101、201、301 酸化物半導体TFT
100A、100B、200A、200B、200C、300 半導体装置
CH1、CH2 コンタクトホール
Claims (15)
- 基板と、
前記基板に支持された薄膜トランジスタであって、ゲート電極、酸化物半導体層、前記ゲート電極と前記酸化物半導体層との間に形成されたゲート絶縁層、および、前記酸化物半導体層の上面と接するソース電極およびドレイン電極を含む薄膜トランジスタと、
前記薄膜トランジスタを覆い、かつ、前記薄膜トランジスタのチャネル領域と接するように配置された層間絶縁層と、
前記層間絶縁層上に配置された透明導電層と
を備え、
前記ソース電極および前記ドレイン電極は、それぞれ、銅層を有し、
前記ソース電極および前記ドレイン電極と前記層間絶縁層との間に配置された銅酸化膜をさらに備え、
前記層間絶縁層は、前記銅酸化膜を介して前記ドレイン電極を覆っており、
前記透明導電層は、前記層間絶縁層に形成された第1のコンタクトホール内で、前記銅酸化膜を介さずに、前記ドレイン電極の前記銅層と直接接している半導体装置。 - 前記銅酸化膜は、前記ソース電極および前記ドレイン電極における前記銅層と接しており、
前記銅層と前記透明導電層との界面は、前記銅層と前記層間絶縁層との界面よりも平坦である請求項1に記載の半導体装置。 - 前記基板の表面の法線方向から見たとき、前記第1のコンタクトホールにおいて、前記銅酸化膜の端部は前記層間絶縁層の端部よりも外側に位置している請求項1または2に記載の半導体装置。
- 前記銅酸化膜の厚さは10nm以上70nm以下である請求項1から3のいずれかに記載の半導体装置。
- 前記銅酸化膜は、前記銅層の表面が酸化処理に曝されることによって形成された酸化膜である請求項1から4のいずれかに記載の半導体装置。
- 前記ソース電極および前記ドレイン電極は、それぞれ、前記銅層の前記基板側に配置され、かつ、前記酸化物半導体層と接する下層をさらに有し、前記下層はチタンまたはモリブデンを含む請求項1に記載の半導体装置。
- 前記基板上に形成された端子部をさらに備え、
前記端子部は、
前記ソース電極および前記ドレイン電極と同一の導電膜から形成されたソース接続層と、
前記ソース配線上に延設された前記層間絶縁層と、
前記透明導電層と同一の透明導電膜から形成された上部導電層と
を有し、
前記ソース接続層の上面の一部は前記銅酸化膜で覆われており、
前記層間絶縁層は、前記銅酸化膜を介して前記ソース接続層を覆っており、
前記上部導電層は、前記層間絶縁層に形成された第2のコンタクトホール内で、前記銅酸化膜を介さずに、前記ソース接続層と直接接している請求項1から6のいずれかに記載の半導体装置。 - 前記ソース電極および前記ドレイン電極と同一の導電膜から形成されたマーク層を有するアライメントマーク部をさらに備え、
前記マーク層の上面の一部は前記銅酸化膜で覆われており、
前記層間絶縁層は、前記銅酸化膜を介して前記マーク層の前記上面の前記一部と接し、かつ、前記マーク層上に開口部を有しており、
前記基板の法線方向から見たとき、前記マーク層の前記上面のうち前記開口部と重なる部分には前記銅酸化膜が配置されていない請求項1から7のいずれかに記載の半導体装置。 - 前記薄膜トランジスタはチャネルエッチ構造を有する請求項1から8のいずれかに記載の半導体装置。
- 前記酸化物半導体層はIn−Ga−Zn−O系半導体を含む請求項1から9のいずれかに記載の半導体装置。
- 前記酸化物半導体層は結晶質部分を含む請求項10に記載の半導体装置。
- (A)基板上に、ゲート電極、ゲート絶縁層、酸化物半導体層、および、銅層を含むソース電極およびドレイン電極を形成することにより薄膜トランジスタを形成する工程と、
(B)前記酸化物半導体層のうち少なくともチャネル領域に対して酸化処理を行う工程であって、これにより、前記少なくともチャネル領域となる部分の表面の酸素濃度を高めるとともに、前記ソース電極およびドレイン電極の表面を酸化して銅酸化膜を形成する、酸化処理工程と、
(C)前記薄膜トランジスタを覆い、かつ、前記チャネル領域と接するように層間絶縁層を形成する工程と、
(D)前記層間絶縁層のうち前記ドレイン電極上に位置する部分に第1のコンタクトホールを形成し、これによって前記銅酸化膜を露出させる、コンタクトホール形成工程と、
(E)キレート洗浄法を用いて、前記銅酸化膜のうち前記第1のコンタクトホールによって露出した部分を除去することにより、前記銅層を露出させる工程と、
(F)前記第1のコンタクトホール内で露出した前記銅層と直接接するように透明導電層を形成する工程と
を包含する半導体装置の製造方法。 - 前記薄膜トランジスタはチャネルエッチ構造を有する請求項12に記載の半導体装置の製造方法。
- 前記酸化物半導体層はIn−Ga−Zn−O系半導体を含む請求項12または13に記載の半導体装置の製造方法。
- 前記酸化物半導体層は結晶質部分を含む請求項14に記載の半導体装置の製造方法。
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TW201626579A (zh) | 2016-07-16 |
TWI619257B (zh) | 2018-03-21 |
JP6259120B2 (ja) | 2018-01-10 |
CN107004719A (zh) | 2017-08-01 |
US20170323907A1 (en) | 2017-11-09 |
US10748939B2 (en) | 2020-08-18 |
WO2016084700A1 (ja) | 2016-06-02 |
CN107004719B (zh) | 2020-07-03 |
US20190109159A1 (en) | 2019-04-11 |
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