JPWO2014020783A1 - 放熱構造を備えた半導体装置 - Google Patents
放熱構造を備えた半導体装置 Download PDFInfo
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- JPWO2014020783A1 JPWO2014020783A1 JP2014527940A JP2014527940A JPWO2014020783A1 JP WO2014020783 A1 JPWO2014020783 A1 JP WO2014020783A1 JP 2014527940 A JP2014527940 A JP 2014527940A JP 2014527940 A JP2014527940 A JP 2014527940A JP WO2014020783 A1 JPWO2014020783 A1 JP WO2014020783A1
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- Prior art keywords
- semiconductor chip
- sealing portion
- semiconductor device
- vias
- semiconductor
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
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Abstract
Description
図1(a)及び図1(b)は、本実施形態に係る半導体装置を模式的に示す断面図と平面図である。
図2(a)及び図2(b)は、本変形例に係る半導体装置を模式的に示す断面図と平面図である。
図3(a)及び図3(b)は、本変形例に係る半導体装置を模式的に示す断面図と平面図である。
図4(a)に示す半導体装置130は、変形例2と同様に、半導体チップ9がワイヤ10によって基板1と電気的に接続されており、さらに、封止部3の表面に配置された放熱体8を備える。この場合も、図4(b)に示すように、外部端子6bは複数のワイヤ10同士の間に配置することができる。この構成により、半導体チップ9に対して、側面方向および裏面方向の、複数の熱の伝導経路が形成されるため、ワイヤボンディング形態の半導体装置130においても、放熱性を向上することが出来る。
図5は、本実施形態に係る半導体装置の実装体を模式的に示す断面図である。
図6は、本変形例に係る半導体装置の実装体を模式的に示す断面図である。
図7(a)及び図7(b)は、本実施形態に係る半導体装置の構成を模式的に示す断面図と平面図である。
図8(a)及び図8(b)は、本変形例に係る半導体装置の構成を模式的に示す断面図と平面図である。
図9は、本実施形態に係る半導体装置の構成を模式的に示す断面図である。
図10は、本変形例に係る半導体装置の構成を模式的に示す断面図である。
図11は、本実施形態に係る半導体装置の構成を模式的に示す断面図である。
図12(a)及び図12(b)は、本実施形態に係る半導体装置の構成を模式的に示す断面図と平面図である。
図13(a)及び図13(b)は、本変形例に係る半導体装置の構成を模式的に示す断面図と平面図である。
図14は、本実施形態に係る半導体装置700の構成を模式的に示す断面図である。
2、9 半導体チップ
3、16 封止部
4 第1のビア
5 第2のビア
6a、6b、6c、6d 外部端子
7 バンプ
8、15、18、19、21a、21b、22、23 放熱体
10 ワイヤ
11 実装基板
12 定電位供給部
13 導電体
14 第3のビア
17 開口部
20a、20b 電子部品
24 再配線
100、110、120、130、300、310、400、410、500、600、610、700 半導体装置
200、210 実装体
Claims (20)
- 第1の面と、前記第1の面と反対側の第2の面を有し、前記第1の面に電極を有する基台と、
前記基台の前記第1の面に搭載された第1の半導体チップと、
前記第1の半導体チップと、前記基台の第1の面を封止した封止部と、
前記封止部の表面から、前記封止部を厚さ方向に貫通し、前記基台の第1の面の前記電極と電気的に接続された複数の第1のビアと、
前記封止部の表面において、前記複数の第1のビアと接続された複数の第1の外部端子と、
前記複数の第1のビアよりも内側に、前記封止部の表面から厚さ方向に前記封止部を貫通しない深さで形成された複数の第2のビアと、
前記封止部の表面において、前記複数の第2のビアと接続された複数の第2の外部端子と
を備え、
前記複数の第2のビアは、前記第1の半導体チップと接触していない
半導体装置。 - 前記複数の第2のビアは、前記基台と接していない
請求項1に記載の半導体装置。 - 前記複数の第2のビアは、前記第1の半導体チップおよび前記基台と絶縁されている
請求項1または2に記載の半導体装置。 - 前記第1の半導体チップの回路形成面は、バンプを介して前記基台の第1の面と電気的に接続されている
請求項1乃至3のいずれか1項に記載の半導体装置。 - 前記第1の半導体チップの回路形成面と反対側の面は、前記基台の第1の面と対向して実装され、
前記第1の半導体チップの前記回路形成面と、前記基台の第1の面の電極とはワイヤを介して電気的に接続されている
請求項1乃至3のいずれか1項に記載の半導体装置。 - 前記複数の第2のビアは、前記第1の半導体チップの裏面近傍に設けられ、一端が前記封止部から露出し、他の一端が前記裏面と対向するよう配置されている
請求項4に記載の半導体装置。 - 前記複数の第2のビアは、前記第1の半導体チップの側面近傍に配置されている
請求項1乃至6のいずれか1項に記載の半導体装置。 - 前記複数の第2のビアは、前記第1の半導体チップの周囲を囲むように配置されている
請求項1乃至7のいずれか1項に記載の半導体装置。 - 前記封止部の、前記基台との接触面とは反対側の表面に配置された第1の放熱体を更に備え、
前記第1の放熱体と前記複数の第2のビアまたは前記複数の第2の外部端子が接続されている
請求項1乃至8のいずれか1項に記載の半導体装置。 - 前記第1の半導体チップの裏面と接触し、前記封止部の内部に配置された第2の放熱体を更に備え、
前記第2の放熱体と前記複数の第2のビアが接続されている
請求項1乃至8いずれか1項に記載の半導体装置。 - 前記第1の放熱体は前記第1の半導体チップの裏面を覆うように配置され、平面視において前記第1の半導体チップの裏面より面積が大きい
請求項9に記載の半導体装置。 - 前記第1の放熱体が導電性材料で構成されている
請求項9又は11に記載の半導体装置。 - 前記封止部に、前記第1の半導体チップの裏面の一部を露出する開口部をさらに備えている
請求項4または6に記載の半導体装置。 - 前記封止部の開口部内に、前記第1の半導体チップの裏面と接触する放熱体をさらに備えている
請求項13記載の半導体装置。 - 前記基台の前記第1の面に搭載され、前記封止部に封止された第2の半導体チップと、
前記封止部の、前記基台との接触面とは反対側の表面に、前記第2の半導体チップの裏面を覆うように配置された第3の放熱体とを更に備え、
第2の半導体チップの側面近傍に、その周囲を囲むように複数の前記第2のビアが配置され、前記第3の放熱体と接続されている
請求項9に記載の半導体装置。 - 前記基台の前記第1の面に搭載され、前記封止部に封止された第1の電子部品をさらに備えている
請求項15に記載の半導体装置。 - 前記封止部の、前記基台との接触面とは反対側の表面に、前記第1の電子部品の裏面を覆うように配置された第4の放熱体を更に備え、
前記第1の電子部品の側面近傍に、その周囲を囲むように複数の前記第2のビアが配置され、前記第4の放熱体と接続されており、
前記第1の半導体チップと前記第2の半導体チップ、前記第2の半導体チップと前記第1の電子部品はそれぞれ隣接して配置されており、
前記第1の半導体チップと前記第2の半導体チップとが対向する辺において、前記第2のビアと第2の外部端子は共有されており、前記第2の半導体チップと前記第1の電子部品とが対向する辺において、前記第2のビアと第2の外部端子は共有されており、
前記第1の放熱体、前記第3の放熱体および前記第4の放熱体は連結形成されている
請求項16に記載の半導体装置。 - 第1の面と、前記第1の面と反対側の第2の面を有し、前記第1の面に電極を有する基台と、
前記基台の前記第1の面に搭載された第1の半導体チップと、
前記第1の半導体チップと、前記基台の第1の面を封止した封止部と、
前記封止部の表面から、前記封止部を厚さ方向に貫通し、前記基台の第1の面の前記電極と電気的に接続された複数の第1のビアと、
前記封止部の表面において、前記複数の第1のビアと接続された複数の第1の外部端子と、
前記複数の第1のビアよりも内側に、前記封止部の表面から厚さ方向に、前記封止部を貫通しない深さで形成された複数の第2のビアと、
前記封止部の、前記基台との接触面とは反対側の表面に配置され、前記第2のビアと接続された第5の放熱体と、
前記第1のビアと前記第2のビアとを接続する導電性の再配線層と
を備え、
前記複数の第2のビアは、前記第1の半導体チップと接触していない
半導体装置。 - 表面に配線パターンが形成された実装基板を備え、
請求項1乃至17のいずれか1項に記載の半導体装置の前記第1の外部端子および第2の外部端子が、前記実装基板の定電位となる電極と電気的に接続されている
半導体装置の実装体。 - 表面に配線パターンが形成された実装基板を備え、
請求項18に記載の半導体装置の前記第1の外部端子が、前記実装基板の定電位となる電極と電気的に接続されている
半導体装置の実装体。
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US9219021B2 (en) | 2015-12-22 |
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