JP2012015192A - 半導体パッケージ及びその製造方法 - Google Patents
半導体パッケージ及びその製造方法 Download PDFInfo
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- JP2012015192A JP2012015192A JP2010147951A JP2010147951A JP2012015192A JP 2012015192 A JP2012015192 A JP 2012015192A JP 2010147951 A JP2010147951 A JP 2010147951A JP 2010147951 A JP2010147951 A JP 2010147951A JP 2012015192 A JP2012015192 A JP 2012015192A
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- upper substrate
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- semiconductor element
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
【解決手段】半導体素子14が搭載された下基板12の上に、スペーサ部材18を介した上基板20を接続する。上基板20の裏面からは、放熱部材24の底面24bを含む部分が突出している。上基板20と下基板1との間の空間にモールド樹脂22を充填して、半導体素子14を樹脂モールドする。放熱部材24の底面24bは、モールド樹脂22に密着している。
【選択図】図1
Description
12 下基板
12a 外部接続パッド
12b 電極接続パッド
12c 接合パッド
14 半導体素子
14a アンダーフィル材
18 銅コアボール
18a はんだ
20 上基板
20a 部品接続パッド
20b 接合パッド
22 モールド樹脂
24 ヒートシンク
24a 上面
24b 底面
24c 溝
30 保護テープ
32 はんだボール
34 半導体素子
36 受動素子
38 ヒートスプレッダ
Claims (10)
- スペーサ部材を介し接続された上基板及び下基板と、
該上基板と該下基板の間に配置され、前記下基板に実装された半導体素子と、
上面が前記上基板の表面で露出し底面が前記半導体素子に対向するように、前記上基板に取り付けられた放熱部材と、
前記上基板と前記下基板との間の空間に充填された樹脂と
を有し、
前記放熱部材の底面は、前記樹脂に密着している半導体パッケージ。 - 請求項1記載の半導体パッケージであって、
前記放熱部材は前記上基板の表面から突出している半導体パッケージ。 - 請求項2記載の半導体パッケージであって、
前記放熱部材の外周に段差が形成されており、当該段差は前記貫通孔の内面に形成された段差又は前記貫通孔と前記上基板の裏面とで形成された段差に係合している半導体パッケージ。 - 請求項1乃至3のうちいずれか一項記載の半導体パッケージであって、
前記放熱部材の前記底面に溝が形成され、該溝の底面と前記半導体素子との間の距離は、前記放熱部材の前記底面と前記半導体素子との間の距離より大きい半導体パッケージ。 - 請求項1乃至4のうちいずれか一項記載の半導体パッケージであって、
前記放熱部材は、前記半導体素子と対向する方向に前記放熱部材を貫通する貫通孔を有し、前記貫通孔内は前記樹脂が配置されている半導体パッケージ。 - 上基板に貫通孔を形成し、
底面が前記上基板の裏面に露出するように該貫通孔に放熱部材を嵌合し、
該放熱部材の前記底面が下基板に搭載された半導体素子に対向するように、前記上基板を前記下基板に対して接続し、
前記上基板と前記下基板との間の空間に樹脂を充填して、前記半導体素子と前記放熱部材とを樹脂モールドする
半導体パッケージの製造方法。 - 請求項6記載の半導体パッケージの製造方法であって、
前記放熱部材を前記上基板から突出させる半導体パッケージの製造方法。 - 請求項7記載の半導体パッケージの製造方法であって、
前記上基板に貫通孔を形成する際に、前記貫通孔の内面に段差を形成し、
前記放熱部材を前記貫通孔に嵌合する際に、前記貫通孔の内面の段差に前記放熱部材の外形の段差を係合させる
半導体パッケージの製造方法。 - 請求項7又は8記載の半導体パッケージの製造方法であって、
前記上基板と前記下基板との間の空間に樹脂を充填する際に、前記放熱部材の前記底面に形成された溝内に前記樹脂を流して前記空間全体に前記樹脂を充填する半導体パッケージの製造方法。 - 請求項6乃至9のうちいずれか一項記載の半導体パッケージの製造方法であって、
前記樹脂モールド工程では、前記放熱部材に形成された貫通孔にも樹脂を配置する半導体パッケージの製造方法。
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JP2012015192A5 JP2012015192A5 (ja) | 2013-05-16 |
JP5437179B2 JP5437179B2 (ja) | 2014-03-12 |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2014020783A1 (ja) * | 2012-07-30 | 2016-07-21 | パナソニック株式会社 | 放熱構造を備えた半導体装置 |
US10381284B2 (en) | 2016-08-26 | 2019-08-13 | Samsung Electro-Mechanics Co., Ltd. | Semiconductor package |
CN111146159A (zh) * | 2018-11-06 | 2020-05-12 | 三星电子株式会社 | 半导体封装件 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004014863A (ja) * | 2002-06-07 | 2004-01-15 | Mitsubishi Electric Corp | 電力用半導体装置 |
JP2004253703A (ja) * | 2003-02-21 | 2004-09-09 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2004363568A (ja) * | 2003-05-09 | 2004-12-24 | Matsushita Electric Ind Co Ltd | 回路素子内蔵モジュール |
JP2009110979A (ja) * | 2007-10-26 | 2009-05-21 | Shinko Electric Ind Co Ltd | 発熱電子部品内装の配線基板及びその製造方法 |
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- 2010-06-29 JP JP2010147951A patent/JP5437179B2/ja active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004014863A (ja) * | 2002-06-07 | 2004-01-15 | Mitsubishi Electric Corp | 電力用半導体装置 |
JP2004253703A (ja) * | 2003-02-21 | 2004-09-09 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2004363568A (ja) * | 2003-05-09 | 2004-12-24 | Matsushita Electric Ind Co Ltd | 回路素子内蔵モジュール |
JP2009110979A (ja) * | 2007-10-26 | 2009-05-21 | Shinko Electric Ind Co Ltd | 発熱電子部品内装の配線基板及びその製造方法 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2014020783A1 (ja) * | 2012-07-30 | 2016-07-21 | パナソニック株式会社 | 放熱構造を備えた半導体装置 |
US10381284B2 (en) | 2016-08-26 | 2019-08-13 | Samsung Electro-Mechanics Co., Ltd. | Semiconductor package |
CN111146159A (zh) * | 2018-11-06 | 2020-05-12 | 三星电子株式会社 | 半导体封装件 |
KR20200052040A (ko) * | 2018-11-06 | 2020-05-14 | 삼성전자주식회사 | 반도체 패키지 |
US11049815B2 (en) | 2018-11-06 | 2021-06-29 | Samsung Electronics Co., Ltd. | Semiconductor package |
KR102554690B1 (ko) | 2018-11-06 | 2023-07-13 | 삼성전자주식회사 | 반도체 패키지 |
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