JPS6419747A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6419747A
JPS6419747A JP17633887A JP17633887A JPS6419747A JP S6419747 A JPS6419747 A JP S6419747A JP 17633887 A JP17633887 A JP 17633887A JP 17633887 A JP17633887 A JP 17633887A JP S6419747 A JPS6419747 A JP S6419747A
Authority
JP
Japan
Prior art keywords
resist
coating agent
insulating film
lower layer
metallic wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17633887A
Other languages
Japanese (ja)
Inventor
Akira Haga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17633887A priority Critical patent/JPS6419747A/en
Publication of JPS6419747A publication Critical patent/JPS6419747A/en
Pending legal-status Critical Current

Links

Landscapes

  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To improve the step coverage on an upper layer metallic wiring while making an insulating film structure in a through hole part equivalent to a single film and taking excellent through hole shape by isotropical and unisotropical two step etching processes by a method wherein only the coating agent on a lower layer metallic wiring is removed. CONSTITUTION:An insulating film 3 is grown on a lower layer metallic wiring 2 patterned on a substrate 1. Furthermore, the film 3 coated with a liquid coating agent 4 is heat treated for setting. After coating a resist, resist opening 7 is provided to expose only the coating agent 4 over the lower layer wiring pattern 2. Next, the other coating agent 11 is removed by short time etching process. Later, the resist 6 is peeled off to grow the second insulating film 5 and then the resist 6 is coated to make the resist opening 7. Finally, isotropical and anisotropical etching processes are performed to enable an excellent through hole shape to be taken due to the absence of silica.
JP17633887A 1987-07-14 1987-07-14 Semiconductor device Pending JPS6419747A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17633887A JPS6419747A (en) 1987-07-14 1987-07-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17633887A JPS6419747A (en) 1987-07-14 1987-07-14 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6419747A true JPS6419747A (en) 1989-01-23

Family

ID=16011837

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17633887A Pending JPS6419747A (en) 1987-07-14 1987-07-14 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6419747A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100353490C (en) * 2004-02-17 2007-12-05 三洋电机株式会社 Semiconductor device manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100353490C (en) * 2004-02-17 2007-12-05 三洋电机株式会社 Semiconductor device manufacturing method

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