JPS6384124A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6384124A
JPS6384124A JP61231456A JP23145686A JPS6384124A JP S6384124 A JPS6384124 A JP S6384124A JP 61231456 A JP61231456 A JP 61231456A JP 23145686 A JP23145686 A JP 23145686A JP S6384124 A JPS6384124 A JP S6384124A
Authority
JP
Japan
Prior art keywords
metal layer
semiconductor chip
brazing material
chip
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61231456A
Other languages
English (en)
Inventor
Katsushi Terajima
克司 寺島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61231456A priority Critical patent/JPS6384124A/ja
Publication of JPS6384124A publication Critical patent/JPS6384124A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
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    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
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    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体チップを搭載する半導体装置に係り、特
にパッケージ基体の半導体チップを搭載する部分の金属
面の構造に関する。
〔従来の技術〕
従来、この神のパッケージの半導体チップラ搭載する部
分は−様な単一平面をもつ金属面となってい友。第６囚
に半導体チップ１を搭載する前のセラミックパッケージ
基体２とロウ材７の断面図を示す。第７図は半導体チッ
１１を搭載した時の断面図である。半導体チップ１ｉＡ
ｕ−８ｉマウントロウ材を介して金属層８に付着させる
。半導体チップをチップ搭載用のＡｕ層部にＡｕ　−Ｍ
　ｉロウ材７を用いて、−スクラブ（引っ掻き）を加え
ながら付着させ、ボンディング金属ワイヤにエフパッケ
ージ基体の内・外電極を結合させることがこの種の半導
体装置の構成である。
〔発明が解決しようとする問題点〕
上述し几従来の半導体装ｔは半導体チップを搭載する部
分の金属層の多くがＡｕ　ｔ−代表とする単一平面層と
なっていた。そこでＡｕ　−８ｉロウ材などを介して、
半導体チップを搭載する時、半導体チップの裏面とパッ
ケージ基体金属層の間にガスなどを含むボイド（９間）
の形成を余儀なくされ、半導体装置としての信頼性を損
ねるという欠点を有してい友。
金ｖ４層のＡｕにセラミックパッケージの基体に通常Ｗ
メタライズｔ−施し、Ｎｉメッキを介して形成されるも
のであるが、ボイドの発生についてはこのチップ搭載部
の金属層の高感が低いことにエフ、外界囲気の巻き込み
、及び水分の存在による還元雰囲気での酸素の発生等が
言われているが、これらを解決し量産をするには多くの
困難がある。ま友、大型化する半導体チップのマウント
性（溶着性）を向上させるべくチップ裏面にＴｉ／Ａｕ
などのメタライズを施した場合のＡｕ　−Ｓ　ｉロウ材
による搭載時には稿状ボイドが発生し易すぐ、ボイドの
回避は高信頼性、高熱放散性の要求には必要なものであ
る。以上の事がセラミックバックージ半導体装置におい
ては重要な問題点であっ几。
〔問題点を解決するための手段〕
本発明の半導体装１１は、半導体チップ搭＠都に細分化
され比金属層パターンを有し、前記金属層パターン上に
半導体チップがロウ付けされていることｆｔ特徴とする
。
〔実施例１〕 次に本発明について図面に基づいて説明する。
第１図は本発明の実施例１の断面図である。セラミック
パッケージ基体２は凹所６に部分的な幾多の金属Ｎ　（
Ｗ／Ｎ　ｉ／Ａｕ　戸ン＜ターン４を有し、Ａｕ−５ｉ
ロウ材７を介して半導体チップを搭載する。第３図はセ
ラミックパッケージ基体凹所６の金属層で本発明に基づ
く細分化された金属面パターン４を示す平面図の一例で
ある。第２図は第３図ＯＡ　−Ｎにおけるセラミックパ
ッケージ基体の断面図である。製造方法の一例ｆ　Ｗ／
Ｎ　ｉ　／Ａｕ層について述べる。まずセラミックパッ
ケージ基体の半導体チップ搭載部に、Ｗ粉を印刷方式で
パターン化して付着させる。次にＮｉ、Ａｕｆｒ、順次
、無！解メッキ方式で形成することにエフ、所望の金属
層パターン間 ンは一辺の長さが０．１〜α５朋になる様に設足すれば
、マウント濡れ性を維持でき、ガス抜きの効果を持ち得
る。厚さは０．０１〜０．１馴を選定すると良い。
〔実施例２〕 第４図は本発明の実施例２の縦断面内である。
基体の半纏体チップ搭載部にアルミナ粉末とガラス粉末
と有機結合剤の混合物を印刷方式で形成して、炉で焼結
し、セラミック（アルミナ）の凹凸パターン′ｔ−作る
。その上に実施例１で述べた方法でＷ／Ｎｉ／Ａｕを形
成し、金属層の最上面がセラミック上面エフも少し高く
なるように形成する。ボイドが形成されにくくなるのは
実施例１と同じ結果で、実施例１エクもさらにセラミッ
ク部とチップの密着強度が強くなり、はがれて不良とな
る率が少なくなる。又、第５図は第３図とは別のパター
ンの例の金属面の細分化したものである。
〔発明の効果〕
以上説明し九工うに本発明はセラミックパッケージ基体
に設けた金、１！ｉ層が細分化された幾多のパターンに
エフ形成され、この金属層が、■ヴ刈／Ａｕという横取
を持つことにより１半導体チップがＭ−８ｉロウ材でス
クラブを介してマウントされればチップ裏面に巻き込ま
れたガスは金属層パターン間の溝を通じチップ裏面外に
排出されることとなる。
特に１大型化されるチップの裏面部れ柱上向上させる為
に、裏面に’ｌ’　ｉ　／ＡＬ！　等のメタライズを施
した場合などはチップ裏面のＡｕをパッケージ基体のＡ
ｕとがＡｕ　−Ｓ　ｉロウ材との槁れが良く、裏面下に
巻き込まれたガスはスクラブを加えても容易に排出され
ない。ここで凹所にある金属層ヲ部分的区切りパターン
による溝を設ければ、ここ工ｆ）滞留し１ガス及び酸化
ロウ材クズはスクラブ及び加圧にエフ、チップ裏面下工
９外に排出することが可能となる。
まｔ１金属層の細分パターン化にエクマウ／ドロウ材の
接着面積は向上し、且つ、加熱によるロウ材の流動、チ
ップの移動を妨ぐことにも効果がある。
【図面の簡単な説明】
第１図は本発明の牛４体装置の第１の実施例の断面因、
第２図はそのセラミックパッケージ基体の断面図、第３
図はセラミックパッケージ基体の金属層り平面図、第４
図は第２の実施例のセラミックパッケージ基体の断面図
、第５図は他の金属層のパターンを示す平面図、纂６図
は従来のセラミックパッケージ基体の断面図、第７図は
従来のセラミックパッケージ基体に半導体テップを搭載
した状態の断面図である。 １・・・半導体チップ、２−・・セラミックパッケージ
基体、３−・・ボンディングワイヤ、４・・・金属Ｋｍ
　（Ｗ／Ｎｉ／Ａｕ）、５・・・蓋材、６・・・凹所、
７　・・−Ａｕ−８ｉｏつ材、７−１．７−２・・・・
・・Ａｕ−８ｉ合金層、８・・・金属層（Ｗ／Ｎｉ　／
Ａｕ）　、９−ボイド。 ／・−°￥″導件チッ７・ 葦　ｌ　　凹 第　２Ｉ！Ｔ ２　・・・セラミツ７ｔ％ｑソγ−ン）６＊４・・・４
メｈ／ｌノＹターン ２・−・凹Ｐ１ 茅　３ｆｆＪ Ｚ・−・」どラミＪｔやＩケー＝；１良本ト４・・・貧
薦肴パｔン 茅　５　図

Claims (1)

    【特許請求の範囲】
  1. 半導体チップ搭載部に細分化された金属層パターンを有
    し、前記金属層パターン上に半導体チップがロウ付けさ
    れていることを特徴とする半導体装置。
JP61231456A 1986-09-29 1986-09-29 半導体装置 Pending JPS6384124A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61231456A JPS6384124A (ja) 1986-09-29 1986-09-29 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61231456A JPS6384124A (ja) 1986-09-29 1986-09-29 半導体装置

Publications (1)

Publication Number Publication Date
JPS6384124A true JPS6384124A (ja) 1988-04-14

Family

ID=16923798

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61231456A Pending JPS6384124A (ja) 1986-09-29 1986-09-29 半導体装置

Country Status (1)

Country Link
JP (1) JPS6384124A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009291803A (ja) * 2008-06-04 2009-12-17 Mitsubishi Materials Corp ボイド発生の少ないＡｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法
JP2014022576A (ja) * 2012-07-18 2014-02-03 Nichia Chem Ind Ltd 半導体素子実装部材及び半導体装置
JP2016184756A (ja) * 2016-06-10 2016-10-20 日亜化学工業株式会社 半導体素子実装部材及び半導体装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009291803A (ja) * 2008-06-04 2009-12-17 Mitsubishi Materials Corp ボイド発生の少ないＡｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法
JP2014022576A (ja) * 2012-07-18 2014-02-03 Nichia Chem Ind Ltd 半導体素子実装部材及び半導体装置
US10068821B2 (en) 2012-07-18 2018-09-04 Nichia Corporation Semiconductor component support and semiconductor device
JP2016184756A (ja) * 2016-06-10 2016-10-20 日亜化学工業株式会社 半導体素子実装部材及び半導体装置

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