JPS6129139A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6129139A
JPS6129139A JP14949584A JP14949584A JPS6129139A JP S6129139 A JPS6129139 A JP S6129139A JP 14949584 A JP14949584 A JP 14949584A JP 14949584 A JP14949584 A JP 14949584A JP S6129139 A JPS6129139 A JP S6129139A
Authority
JP
Japan
Prior art keywords
semiconductor device
copper
pellet
bonding
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14949584A
Other languages
English (en)
Inventor
Masatoshi Seki
関　正俊
Kanji Otsuka
寛治 大塚
Masayuki Shirai
優之 白井
Kunizo Sawara
佐原　邦造
Ken Okuya
謙 奥谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14949584A priority Critical patent/JPS6129139A/ja
Publication of JPS6129139A publication Critical patent/JPS6129139A/ja
Pending legal-status Critical Current

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  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔技術分野〕 本発明は、半導体装置の電気的接続に適用して有効な技
術に関するものである。
〔背景技術〕
ペレットのボンディングパッドと外部端子等との電気的
接続方法にワイヤボンディング法がある。
ワイヤボンディング法では、安価なアルミニウム製のワ
イヤを用いることができるが、ボンディングパッドも通
常アルミニウムで形成されているため腐食を受は易いと
いう問題があり、また、金に比べ電気抵抗が大きいため
、大きな電流密度を得難いという問題もある。後者の問
題は大電流を必要とする大型の高集積度ペレットや複数
のペレットが取り付けられている、いわゆるマザーチッ
プに適用する場合には特に重要となる。
そこで、金に電気抵抗が近くかつアルミニウムに比べ耐
食性の高い銅からなるワイヤ、それも９９．９９重量パ
ーセント以上の高純度の銅で形成されているワイヤを用
いることが考えられる。このように高純度の銅ワイヤを
用いることにより、いわゆるボールボンディングを行な
うことが可能となる。
ところが、前記の如く銅ワイヤで電気的接続を行なう場
合は１通常アルミニウム製ワイヤに適用されるアルミニ
ウムからなるボンディングパッドを、そのまま利用でき
ないという問題がある。
なお、ワイヤボンディング技術の概略については、たと
えば工業調査会１９８０年１月１５日発行、ｒＩＣ化実
装技術」（日本マイクロエレクトロニクス協会編）、Ｐ
１０１〜Ｐ１０２に示されている。
〔発明の目的〕
本発明の目的は、半導体装置の電気的接続に適用して有
効な技術を提供することにある。
本発明の他の目的は、電気的接続に関し半導体装置の性
能向上に適用して有効な技術を提供することにある。
本発明の他の目的は、半導体装置の製造の合理化に適用
して有効な技術を提供することＫもある。
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。
〔発明の概要〕
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。
すなわち、ペレットのボンディングパッドの最上層を金
で形成することにより、銅ワイヤの接続を可能ならしむ
ることにより、該パッドと銅ワイヤとの確実な接続を行
うと同時に、大電流の供給をも可能とするものである。
また、フェースダウンボンディングにてペレットが取り
付けられてなるマザーチップにおいては、ペレット取付
電極とボンディングパッドとをほぼ同一構造で形成する
ことができることにより、両者を同一工程で形成するこ
とが可能となるものである。
〔実施例〕
第１図は本発明による一実施例である半導体装置の特徴
を、その部分断面図で示したものである。
第２図は本実施例の半導体装置の概略を、そのほぼ中心
を切る第１図と同一面における断面図で示したものであ
る。
第２図に示す如く、本実施例の半導体装置はシリコンカ
ーバイドを主成分とする材料からなる基板１上に、図面
上２つのペレット２が半田からなルハンブを極３でフェ
ースダウノボンデインクサれているマザーチップ４が、
金−シリコン共晶５で取り付けられ、該マザーチップ４
の周囲の基板１上面には４２−アロイ、銅または銅合金
等からなるリード６が拡散接合などにより接合され、該
リード内端部とマザーチップ４のボンディングパッドと
が純度９９．９９重量パーセント以上の銅ワイヤ７で電
気的に接続され、さらに前記ペレット等がムライトから
なる断面コ字状のキャップ８を基板１上面周囲に低融点
ガラス９を介して取り付げることＫより封止されてなる
ものである。ここで、ペレット２およびマザーチップ４
はともにシリコンで形成されてなるものである。
第１図に示す如く、本実施例工の半導体装置の特徴は、
高純度銅ワイヤがボールボンディングされているボンデ
ィングパッド１０とペレット２のバンプ電極３が接続さ
れているペレット取付用電極１０が同一構造で形成され
ていることにある。
すなわち、パッド１０および電極１１は、マザーチップ
４の絶縁膜１２上に形成されているアルミニウム配線１
３の一部を該配線１３上に形成されている窒化ケイ素等
からなるファイナルパッシベーション膜１４を穿孔し、
露出せしめた後、第１層１０ａ、Ｉｌａとしてクロム、
第２層１０ｂ。
１１ｂとして銅、さらに第３層１０ｃ、ｌｌｃとして金
をそれぞれ蒸着等の方法で被着して形成されてなるもの
である。
パッド１０を以上説明した如き構造にすることにより、
銅製のワイヤ７をボールボンディングで強固に取り付け
ることが可能となり、ワイヤ７およびパッド１０の耐食
性向上も可能となるものである。
また、パッド１０と電極１１とを同一工程で形成できる
効果もある。
〔効果〕
（１）最上層が金で形成されてなるペレットのボンディ
ングパッドに銅ワイヤを接続することにより、強固な取
り付けが可能となる。
（２１９９，９９重量パーセント以上の高純度銅ワイヤ
を用いることにより、通常のポールボンディング法にて
容易に接続することが可能である。
（３）ボンディングパッドを第１層にクロム、第２層に
銅、第３層に金をそれぞれ被着して形成することにより
、銅ワイヤとの接続に適したものを提供できる。
（４）前記（３）によりアルミニウムワイヤを使用する
場合に比べ、ワイヤおよびパッドの耐食性を向上させる
ことができるので、信頼性の高い半導体装置を提供でき
る。
（５）　　前記（４）により、大電流を供給できる信頼
性の高い半導体装置を提供できる。
（６）　　フェースダウンボンディングでベレットカ取
り付けられているマザーチップのボンディングパッドを
、前記（１）または（３）に記載の構造にすることによ
り、ペレット取付電極と同一構造にすることができるの
で該取付電極と同一工程で形成することができる。
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもないＯ たとえば、ボンディングパッドの構造はペレット上面に
順次り四ム、銅および金を被着してなる３層構造に限る
ものでなく、チタン、銅および金の３層構造等の如く最
上層の全以外を他の金属で形成したものであってもよい
。
□、＜Ｌ／２）、よ７ｚ−２／”つ：ｙｙｙｙｆ＜ｙｙ
　　　　　　’でペレットを取り付けるマザーチップに
限るものでなく、ワイヤボンディングで取り付けられて
いるペレットと電気的接続を行なうマザーチップであっ
ても良（、通常のペレットに適用することができること
も言うまでもない。
〔利用分野〕
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である基板がシリコンカー
バイト・を主成分とする材料であるセラミックで形成さ
れてなるフラットパッケージ型半導体装置に適用した場
合について説明したが、それに限定されるものではなく
、たとえば、基板をアルミナ等の通常使用されるセラミ
ックで形成したものであっても、またパッケージの型も
ＤＩＰ型等の種々のものに適用できることは言うまでも
ない。
また、パッケージ材料はセラミックに限られるものでな
く、樹脂を材料として形成される、たとえば樹脂封止型
半導体装置に適用しても有効な技術であることは言うま
でもない。
【図面の簡単な説明】
第１図は、本発明による一実施例である半導体装置の特
徴を示す部分拡大断面図、 ・第２図は、本実施例の半導体装置の全体的な概略を示
す断面図である。 １・・・基板、２・・・ペレット、３・・・バンプ電極
、４・・・マザーチップ、５・・・金−シリコン共晶、
６・・・リード、７・・・ワイヤ、８・・・キャップ、
９・・・低融点ガラス、１０・・・取付電極、１０ａ、
Ｉｌａ・・・第１層、１０ｂ、ｌｌｂ・・・第２層、１
０ｃ、ｌｌｃ・−第３層、１２・・・絶縁膜、１３・・
・配線、１４・・・ファイナルパッシベーション膜。

Claims (1)

  1. 【特許請求の範囲】 １、ペレット上面周囲に最上層が金で形成されているボ
    ンディングパッドを備え、該ボンディングパッドと外部
    端子とが銅ワイヤで接続されてなる半導体装置。 ２、ボンディングパッドがペレット表面配線上にクロム
    、銅および金を順次被着した３層で形成されていること
    を特徴とする特許請求の範囲第１項記載の半導体装置。 ３、ワイヤが９９．９９重量パーセント以上の純度の銅
    で形成されていることを特徴とする特許請求の範囲第１
    項記載の半導体装置。 ４、ペレットがその上面に２以上のペレットがフェース
    ダウンボンディングされているマザーチップであること
    を特徴とする特許請求の範囲第１項記載の半導体装置。 ５、パッケージ基板がシリコンカーバイドを主成分とす
    る材料で形成されていることを特徴とする特許請求の範
    囲第１項記載の半導体装置。 ６、外部端子が基板上面に拡散接合で取り付けられてい
    ることを特徴とする特許請求の範囲第１または第５項記
    載の半導体装置。
JP14949584A 1984-07-20 1984-07-20 半導体装置 Pending JPS6129139A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14949584A JPS6129139A (ja) 1984-07-20 1984-07-20 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14949584A JPS6129139A (ja) 1984-07-20 1984-07-20 半導体装置

Publications (1)

Publication Number Publication Date
JPS6129139A true JPS6129139A (ja) 1986-02-10

Family

ID=15476394

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14949584A Pending JPS6129139A (ja) 1984-07-20 1984-07-20 半導体装置

Country Status (1)

Country Link
JP (1) JPS6129139A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5455195A (en) * 1994-05-06 1995-10-03 Texas Instruments Incorporated Method for obtaining metallurgical stability in integrated circuit conductive bonds
EP1367644A1 (en) * 2002-05-29 2003-12-03 STMicroelectronics S.r.l. Semiconductor electronic device and method of manufacturing thereof
JP2012069691A (ja) * 2010-09-22 2012-04-05 Toshiba Corp 半導体装置とその製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5455195A (en) * 1994-05-06 1995-10-03 Texas Instruments Incorporated Method for obtaining metallurgical stability in integrated circuit conductive bonds
EP1367644A1 (en) * 2002-05-29 2003-12-03 STMicroelectronics S.r.l. Semiconductor electronic device and method of manufacturing thereof
JP2012069691A (ja) * 2010-09-22 2012-04-05 Toshiba Corp 半導体装置とその製造方法

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