JPS6362063A - 非同期通信制御回路 - Google Patents

非同期通信制御回路

Info

Publication number
JPS6362063A
JPS6362063A JP20595886A JP20595886A JPS6362063A JP S6362063 A JPS6362063 A JP S6362063A JP 20595886 A JP20595886 A JP 20595886A JP 20595886 A JP20595886 A JP 20595886A JP S6362063 A JPS6362063 A JP S6362063A
Authority
JP
Japan
Prior art keywords
dma
signal
request signal
controller
dma request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20595886A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0437458B2 (https=
Inventor
Mineo Tateno
舘野　峰夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP20595886A priority Critical patent/JPS6362063A/ja
Publication of JPS6362063A publication Critical patent/JPS6362063A/ja
Publication of JPH0437458B2 publication Critical patent/JPH0437458B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP20595886A 1986-09-03 1986-09-03 非同期通信制御回路 Granted JPS6362063A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20595886A JPS6362063A (ja) 1986-09-03 1986-09-03 非同期通信制御回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20595886A JPS6362063A (ja) 1986-09-03 1986-09-03 非同期通信制御回路

Publications (2)

Publication Number Publication Date
JPS6362063A true JPS6362063A (ja) 1988-03-18
JPH0437458B2 JPH0437458B2 (https=) 1992-06-19

Family

ID=16515519

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20595886A Granted JPS6362063A (ja) 1986-09-03 1986-09-03 非同期通信制御回路

Country Status (1)

Country Link
JP (1) JPS6362063A (https=)

Also Published As

Publication number Publication date
JPH0437458B2 (https=) 1992-06-19

Similar Documents

Publication Publication Date Title
JPH01237864A (ja) Ｄｍａ転送制御装置
US5287486A (en) DMA controller using a programmable timer, a transfer counter and an or logic gate to control data transfer interrupts
JPS6152507B2 (https=)
JPS6362063A (ja) 非同期通信制御回路
JPS6347864A (ja) メモリ間のデ−タ転送方法
JPS61271555A (ja) ダイレクトメモリアクセス転送方式
JPH03769Y2 (https=)
JPS6142649U (ja) デ−タ転送装置
JPS58154030A (ja) Ｄｍａ制御方式
JPS599306Y2 (ja) デ−タ処理装置
JPS61151746A (ja) デ−タエラ−の処理方法
JPS5994159A (ja) デ−タ転送制御方式
JPS5887612A (ja) 入出力制御診断装置
JPH0273447A (ja) ローカルｃｐｕのログオン方法
JPH05265925A (ja) データ転送制御装置
JPS60136853A (ja) デ−タ転送方式
JPS5851293B2 (ja) デ−タ交換制御方式
JPH05282239A (ja) Ｄｍａ転送方式
JPS5916035A (ja) コンピユ−タにおけるｄｍａ方式
JPS62175855A (ja) Ｉ／ｏインタフエ−ス
JPS58167938U (ja) プリンタ装置
JPH01126749A (ja) 周辺機器データ制御装置
JPS5897605U (ja) マルチプロセツサによるバツチプロセス用コントロ−ラ
JPS5836453U (ja) マルチ計算機システムにおけるプログラム動作メモリの有効活用機構
JPS62160546A (ja) デ−タベ−スの管理方式

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term