JPH0437458B2 - - Google Patents

Info

Publication number
JPH0437458B2
JPH0437458B2 JP20595886A JP20595886A JPH0437458B2 JP H0437458 B2 JPH0437458 B2 JP H0437458B2 JP 20595886 A JP20595886 A JP 20595886A JP 20595886 A JP20595886 A JP 20595886A JP H0437458 B2 JPH0437458 B2 JP H0437458B2
Authority
JP
Japan
Prior art keywords
dma
signal
request signal
dma controller
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP20595886A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6362063A (ja
Inventor
Mineo Tateno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP20595886A priority Critical patent/JPS6362063A/ja
Publication of JPS6362063A publication Critical patent/JPS6362063A/ja
Publication of JPH0437458B2 publication Critical patent/JPH0437458B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP20595886A 1986-09-03 1986-09-03 非同期通信制御回路 Granted JPS6362063A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20595886A JPS6362063A (ja) 1986-09-03 1986-09-03 非同期通信制御回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20595886A JPS6362063A (ja) 1986-09-03 1986-09-03 非同期通信制御回路

Publications (2)

Publication Number Publication Date
JPS6362063A JPS6362063A (ja) 1988-03-18
JPH0437458B2 true JPH0437458B2 (https=) 1992-06-19

Family

ID=16515519

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20595886A Granted JPS6362063A (ja) 1986-09-03 1986-09-03 非同期通信制御回路

Country Status (1)

Country Link
JP (1) JPS6362063A (https=)

Also Published As

Publication number Publication date
JPS6362063A (ja) 1988-03-18

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term