JPS6346453B2 - - Google Patents

Info

Publication number
JPS6346453B2
JPS6346453B2 JP53163883A JP16388378A JPS6346453B2 JP S6346453 B2 JPS6346453 B2 JP S6346453B2 JP 53163883 A JP53163883 A JP 53163883A JP 16388378 A JP16388378 A JP 16388378A JP S6346453 B2 JPS6346453 B2 JP S6346453B2
Authority
JP
Japan
Prior art keywords
processing
address
storage device
contents
function
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53163883A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5588141A (en
Inventor
Keiichi Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16388378A priority Critical patent/JPS5588141A/ja
Publication of JPS5588141A publication Critical patent/JPS5588141A/ja
Publication of JPS6346453B2 publication Critical patent/JPS6346453B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP16388378A 1978-12-27 1978-12-27 Microprogram control system Granted JPS5588141A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16388378A JPS5588141A (en) 1978-12-27 1978-12-27 Microprogram control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16388378A JPS5588141A (en) 1978-12-27 1978-12-27 Microprogram control system

Publications (2)

Publication Number Publication Date
JPS5588141A JPS5588141A (en) 1980-07-03
JPS6346453B2 true JPS6346453B2 (cg-RX-API-DMAC7.html) 1988-09-14

Family

ID=15782598

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16388378A Granted JPS5588141A (en) 1978-12-27 1978-12-27 Microprogram control system

Country Status (1)

Country Link
JP (1) JPS5588141A (cg-RX-API-DMAC7.html)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56152049A (en) * 1980-04-25 1981-11-25 Toshiba Corp Microprogram control system
JP2672599B2 (ja) * 1988-10-18 1997-11-05 ヤマハ 株式会社 コンピュータシステム

Also Published As

Publication number Publication date
JPS5588141A (en) 1980-07-03

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