JPS6341103B2 - - Google Patents

Info

Publication number
JPS6341103B2
JPS6341103B2 JP57145156A JP14515682A JPS6341103B2 JP S6341103 B2 JPS6341103 B2 JP S6341103B2 JP 57145156 A JP57145156 A JP 57145156A JP 14515682 A JP14515682 A JP 14515682A JP S6341103 B2 JPS6341103 B2 JP S6341103B2
Authority
JP
Japan
Prior art keywords
cpu
microprocessor
access
line
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57145156A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5935267A (ja
Inventor
Hisao Sakamoto
Takuya Sugita
Kimiko Shima
Katsuhide Tsukamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57145156A priority Critical patent/JPS5935267A/ja
Publication of JPS5935267A publication Critical patent/JPS5935267A/ja
Publication of JPS6341103B2 publication Critical patent/JPS6341103B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP57145156A 1982-08-20 1982-08-20 マルチマイクロプロセツサ Granted JPS5935267A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57145156A JPS5935267A (ja) 1982-08-20 1982-08-20 マルチマイクロプロセツサ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57145156A JPS5935267A (ja) 1982-08-20 1982-08-20 マルチマイクロプロセツサ

Publications (2)

Publication Number Publication Date
JPS5935267A JPS5935267A (ja) 1984-02-25
JPS6341103B2 true JPS6341103B2 (en:Method) 1988-08-15

Family

ID=15378716

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57145156A Granted JPS5935267A (ja) 1982-08-20 1982-08-20 マルチマイクロプロセツサ

Country Status (1)

Country Link
JP (1) JPS5935267A (en:Method)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62150459A (ja) * 1985-12-24 1987-07-04 Nec Corp シングルチツプマイクロコンピユ−タ
DE3632500A1 (de) * 1986-09-24 1988-04-07 Fresenius Ag Zentrifugenanordnung
US5229586A (en) * 1988-10-28 1993-07-20 Tokyo Electric Co., Ltd. Card issuing apparatus having sequential processing units
US5870497A (en) * 1991-03-15 1999-02-09 C-Cube Microsystems Decoder for compressed video signals

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54120511A (en) * 1978-03-11 1979-09-19 Nippon Telegr & Teleph Corp <Ntt> Reception system for digital multi-frequency signal

Also Published As

Publication number Publication date
JPS5935267A (ja) 1984-02-25

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