JPS6337418B2 - - Google Patents

Info

Publication number
JPS6337418B2
JPS6337418B2 JP58219094A JP21909483A JPS6337418B2 JP S6337418 B2 JPS6337418 B2 JP S6337418B2 JP 58219094 A JP58219094 A JP 58219094A JP 21909483 A JP21909483 A JP 21909483A JP S6337418 B2 JPS6337418 B2 JP S6337418B2
Authority
JP
Japan
Prior art keywords
dma
bus
cpu
controller
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58219094A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60110067A (ja
Inventor
Shunji Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP21909483A priority Critical patent/JPS60110067A/ja
Publication of JPS60110067A publication Critical patent/JPS60110067A/ja
Publication of JPS6337418B2 publication Critical patent/JPS6337418B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP21909483A 1983-11-21 1983-11-21 簡易型メモリデ−タ転送装置 Granted JPS60110067A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21909483A JPS60110067A (ja) 1983-11-21 1983-11-21 簡易型メモリデ−タ転送装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21909483A JPS60110067A (ja) 1983-11-21 1983-11-21 簡易型メモリデ−タ転送装置

Publications (2)

Publication Number Publication Date
JPS60110067A JPS60110067A (ja) 1985-06-15
JPS6337418B2 true JPS6337418B2 (enrdf_load_stackoverflow) 1988-07-25

Family

ID=16730161

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21909483A Granted JPS60110067A (ja) 1983-11-21 1983-11-21 簡易型メモリデ−タ転送装置

Country Status (1)

Country Link
JP (1) JPS60110067A (enrdf_load_stackoverflow)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6484942A (en) * 1987-09-25 1989-03-30 Nec Corp Packet buffer control system
US7284082B2 (en) * 2004-08-19 2007-10-16 Lsi Corporation Controller apparatus and method for improved data transfer

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55150032A (en) * 1979-05-14 1980-11-21 Fujitsu Ltd Data transfer system
JPS564826A (en) * 1979-06-25 1981-01-19 Matsushita Electric Ind Co Ltd Electronic computer
JPS5759220A (en) * 1980-09-26 1982-04-09 Toshiba Corp Data transfer system

Also Published As

Publication number Publication date
JPS60110067A (ja) 1985-06-15

Similar Documents

Publication Publication Date Title
US4528626A (en) Microcomputer system with bus control means for peripheral processing devices
JPS5837585B2 (ja) ケイサンキソウチ
JPH0554144B2 (enrdf_load_stackoverflow)
JPS6337418B2 (enrdf_load_stackoverflow)
JP3014494B2 (ja) デュアルポートディスク制御装置
US5446847A (en) Programmable system bus priority network
JPH0343804A (ja) シーケンス制御装置
JPS6142293B2 (enrdf_load_stackoverflow)
JP2607073B2 (ja) 演算処理装置
JP2619385B2 (ja) Ｄｍａコントローラ
JP2555580B2 (ja) 記憶装置制御方式
JP2705955B2 (ja) 並列情報処理装置
JPS6029139B2 (ja) 処理装置間結合方式
JPS60136853A (ja) デ−タ転送方式
JPH0142017B2 (enrdf_load_stackoverflow)
JPS61234447A (ja) バス獲得制御装置
EP0373393A1 (en) Information processing system
JPH03282954A (ja) ダイレクトメモリアクセスデータ転送装置
JPH0575140B2 (enrdf_load_stackoverflow)
JPH02211571A (ja) 情報処理装置
JPH04276845A (ja) バス調停回路
JPS60118967A (ja) マルチプロセツサシステム
JPS61131152A (ja) Ｄｍａバツフア制御方式
JPH03226850A (ja) 外部補助記憶制御装置
JPH0650494B2 (ja) 入出力制御装置におけるデータ転送方式