JPS6242395B2 - - Google Patents

Info

Publication number
JPS6242395B2
JPS6242395B2 JP56075185A JP7518581A JPS6242395B2 JP S6242395 B2 JPS6242395 B2 JP S6242395B2 JP 56075185 A JP56075185 A JP 56075185A JP 7518581 A JP7518581 A JP 7518581A JP S6242395 B2 JPS6242395 B2 JP S6242395B2
Authority
JP
Japan
Prior art keywords
region
forming
type
conductivity type
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56075185A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57190348A (en
Inventor
Shuichi Kameyama
Koichi Kanzaki
Yoshitaka Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP56075185A priority Critical patent/JPS57190348A/ja
Priority to US06/378,480 priority patent/US4433470A/en
Publication of JPS57190348A publication Critical patent/JPS57190348A/ja
Publication of JPS6242395B2 publication Critical patent/JPS6242395B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H10P32/1414—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates

Landscapes

  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
JP56075185A 1981-05-19 1981-05-19 Manufacture of bipolar semiconductor device Granted JPS57190348A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP56075185A JPS57190348A (en) 1981-05-19 1981-05-19 Manufacture of bipolar semiconductor device
US06/378,480 US4433470A (en) 1981-05-19 1982-05-14 Method for manufacturing semiconductor device utilizing selective etching and diffusion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56075185A JPS57190348A (en) 1981-05-19 1981-05-19 Manufacture of bipolar semiconductor device

Publications (2)

Publication Number Publication Date
JPS57190348A JPS57190348A (en) 1982-11-22
JPS6242395B2 true JPS6242395B2 (enExample) 1987-09-08

Family

ID=13568886

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56075185A Granted JPS57190348A (en) 1981-05-19 1981-05-19 Manufacture of bipolar semiconductor device

Country Status (1)

Country Link
JP (1) JPS57190348A (enExample)

Also Published As

Publication number Publication date
JPS57190348A (en) 1982-11-22

Similar Documents

Publication Publication Date Title
US4433470A (en) Method for manufacturing semiconductor device utilizing selective etching and diffusion
JP3132101B2 (ja) 半導体装置の製造方法
US4408387A (en) Method for producing a bipolar transistor utilizing an oxidized semiconductor masking layer in conjunction with an anti-oxidation mask
JPS6252963A (ja) バイポ−ラトランジスタの製造方法
JPH0241170B2 (enExample)
JPS5936432B2 (ja) 半導体装置の製造方法
JPS6242395B2 (enExample)
JPS6242396B2 (enExample)
JPS6242397B2 (enExample)
JP2663632B2 (ja) 半導体装置及びその製造方法
JPS5984469A (ja) 半導体装置の製造方法
JP2528559B2 (ja) ラテラルバイポ―ラトランジスタの製造方法
JP2817210B2 (ja) 半導体装置の製造方法
JP3260549B2 (ja) バイポーラ型半導体集積回路装置の製造方法
JPH07142505A (ja) 半導体装置の製造方法
JPS629226B2 (enExample)
JPS6232628B2 (enExample)
JPS627704B2 (enExample)
JPS6032349B2 (ja) 半導体装置の製造方法
JP2606648B2 (ja) バイポーラトランジスタ及びその製造方法
JPS58142573A (ja) 半導体集積回路およびその製造方法
JP3131986B2 (ja) バイポーラトランジスタ
JP2915002B2 (ja) バイポーラ型半導体集積回路装置及びその製造方法
JPH05275633A (ja) 半導体装置及びその製造方法
JPH05109745A (ja) 半導体装置