JPS6242395B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a bipolar semiconductor device, and particularly to a method for manufacturing a bipolar integrated circuit having an I ² L element.

I ² L (Integrated Injection Logic) has a composite structure of an inverted vertical transistor (e.g. npn transistor) and a complementary lateral transistor (pnp transistor) whose collector is the base of this transistor. It is a logic element. In such I ² L, the lateral transistor acts as an injector that injects charge into the base of the vertical transistor with the reverse structure, and the vertical transistor with the reverse structure operates as an inverter. For this reason, I ² L has attracted attention in recent years as an element that has a small logic amplitude and can operate at high speed and with low power consumption. Furthermore, since I ₂ L does not require isolation between vertical transistors and lateral transistors, it has a high degree of integration and is suitable for large-scale integrated circuit applications. Furthermore, since I ² L is a bipolar process technology, it is easy to integrate other bipolar circuits, such as linear circuits and ECL circuits, on the same chip.
(Emitter Coupled Logic) can coexist, making it possible to realize multifunctional integrated circuits.

By the way, a lot of research has been done to make the above-mentioned I ² L operate at high speed. For example, IEEE
Journal of Solid-State Circuita, Vol, SC-
14, No. 2, April 1979, 327-336. In order to reduce the accumulation of minority carriers,
In addition to optimizing the concentration profile of the epitaxial semiconductor layer and the emitter layer, it is effective to minimize the area where minority carriers are accumulated. From this point of view, it has been conventionally considered to produce I ² L by the following method. That is, after selectively forming an n ⁺ buried layer 2 on a p-type silicon substrate 1 and growing an n-type epitaxial layer 3 on the same substrate 1, a thick field oxide film 4 for device isolation is selected. Formed by oxidation technology.
Subsequently, after selectively covering the SiO ₂ film 5 on the element forming region by CVD method or photolithography method, this SiO ₂ film 5 is
Boron is thermally diffused using the film 5 as a mask to form a p-type base region 6 and an injector 7 (as shown in FIG. 1A). Next, a polycrystalline silicon film doped with arsenic, which is an n-type impurity, is deposited on the entire surface.
This is patterned and the polycrystalline silicon film is selectively etched to form polycrystalline silicon patterns 8a and 8b on the portion where the collector region is to be formed (first
(Figure b shown). Subsequently, high-temperature thermal oxidation treatment is performed to form a thick silicon thermal oxide film 9 around the polycrystalline silicon patterns 8a and 8b, a thin silicon thermal oxide film 1 on the exposed base region 6, and the injector 7.
At the same time, arsenic is diffused from the arsenic-doped polycrystalline silicon patterns 8a and 8b into the p-type base region 6 to form the n ⁺ -type collector region 11.
a, 11b are formed. After that, the thin silicon thermal oxide film 10 is removed by etching, and the polycrystalline silicon pattern insulated by the thick silicon thermal oxide film 9 is used as the collector lead-out electrodes 12a, 12b, and then an Al film is deposited on the entire surface to form the field oxide film. 4
And by patterning on the SiO ₂ film 5, a base lead-out Al electrode 13 and an injector lead-out Al electrode 14 are formed.
to form an integrated circuit containing I ² L (first step
Figure c). In the figure, 15a to 15c are base contact parts, and 16 is an injector contact part.

In manufacturing an integrated circuit including the above-mentioned I ² L, the base contact hole can be opened in a self-aligned manner with respect to the collector lead-out electrodes 12a and 12b of arsenic-doped polycrystalline silicon,
can be brought into contact with the base region 6 over a wide area.
Furthermore, the area of the base region 6 can be made smaller than the area of the collector regions 11a and 11b. Therefore, the speed of the obtained I ² L can be increased, and the current amplification factor (h _FE ) can be improved by increasing the area ratio of collector to base (S _C /S _B ), and furthermore, it is possible to improve the integration You can improve your degree. however,
In the case of I ² L having such a structure, as shown in FIG. 1c, the base contact portion 15a of the npn transistor
The pn junction directly under ~15c is the collector region 11
It acts as a parasitic to the base-emitter pn junction of the intrinsic npn transistor directly below a and 11b. Such a parasitic pn junction deteriorates the collector-to-base ratio (S _C /S _B ) of the npn transistor during DC operation, thereby reducing the current amplification factor of the npn transistor and reducing the fan-out capability. Moreover, in the switching operation, minority carriers are accumulated in the n-type epitaxial layer of the parasitic diode, increasing the diffusion capacitance, thereby impairing the high-speed operation of the I ² L gate.

In order to prevent the above-mentioned parasitic junction, a silicon oxide body 17 is placed directly under the base contact portions 15a to 15c of the npn transistor as shown in FIG.
I ² L having a structure in which a to 17c are embedded is known. Note that 17d is a silicon oxide buried in a portion directly below the contact portion 16 of the injector 7. Although such a structure can prevent the formation of a parasitic pn junction, it has various drawbacks in terms of manufacturing method as described below.

(a) The silicon oxide bodies 17a to 17d are formed on the n ⁺ buried layer 2, but in the subsequent growth of the n type epitaxial layer 3, the silicon oxide bodies 17a to 17d and their vicinity are The semiconductor layer tends to become polycrystalline, which deteriorates the characteristics of transistors formed near the silicon oxide bodies 17a to 17d.

(b) npn for silicon oxides 17a to 17c
Since it is necessary that the base regions 6 of the transistors are in contact with each other, the thickness of the n-type epitaxial layer 3 is limited to about the depth of the base region 6 of the npn transistor.

(c) Collector region 11a, 1 of npn transistor
Arsenic-doped polycrystalline silicon patterns 8a and 8b and silicon oxides 17a to 1b serve as diffusion sources
Since alignment with silicon oxide 17c needs to be performed by mask alignment, silicon oxide body 17a
Collector regions 11a, 11b for ~17c
cannot be self-aligned, and as a result,
This results in a decrease in the degree of integration.

Therefore, as described above, silicon oxide is first buried and an epitaxial layer is formed on it.
The method of making I ² L gates has structural and performance problems.

On the other hand, the intrinsic
One possible method for forming an npn transistor is to selectively epitaxially grow the region that will become the intrinsic transistor portion, but selective epitaxial growth is not necessarily suitable as a mass production technology at present.

The present invention has been made to solve the above-mentioned drawbacks, and is capable of easily and mass-producing the formation of parasitic pn junctions without being subject to limitations such as deterioration of the crystallinity of the epitaxial layer or the depth of the base region of the npn transistor. The purpose of this invention is to provide a method for manufacturing bipolar semiconductor devices such as I ² L that prevents this.

That is, in the present invention, after forming a first impurity region of a second conductivity type in a surface layer or a part of the interior of a semiconductor layer of a first conductivity type, a first impurity region is formed in the semiconductor layer within or on the first impurity region. forming a second impurity region of a conductivity type; forming a conductor pattern containing an impurity of the first conductivity type on the semiconductor layer in which at least the second impurity region is located; and forming a conductor pattern on an exposed surface of the conductor pattern. a step of selectively forming an insulating film; and using the insulating film as a mask, selectively etching the semiconductor layer to a depth comparable to that of the first impurity region to form a vertical layer including the first impurity region and the second impurity region; Alternatively, a step of forming a protruding semiconductor region with nearly vertical side surfaces, selectively forming an oxidation-resistant insulating film on the side surfaces of the protruding semiconductor region, and then performing thermal oxidation treatment to expose the etched portion. forming an oxide film on the bottom surface; and after removing the oxidation-resistant insulating film, forming an electrode on the protruding semiconductor region to be connected to the first impurity region of the second conductivity type through its side surface. It is characterized by having the following.

In the present invention, the means for forming the first impurity region of the second conductivity type in the semiconductor layer of the first conductivity type is as follows:
For example, a method of providing a glass layer containing impurities of the second conductivity type in a desired region on the semiconductor layer and performing thermal diffusion using this as a diffusion source, a method of selectively ion-implanting the impurities of the second conductivity type, or the like may be adopted. If the latter ion implantation method is adopted, it is also possible to form the first impurity region in a part of the inside of the semiconductor layer.

In the present invention, as a means for forming the second impurity region of the first conductivity type in a part of the semiconductor layer within or on the first impurity region, for example, after masking the area other than the part where the second impurity region is to be formed, A method of ion-implanting or thermally diffusing an impurity of the first conductivity type, or using a conductor pattern containing the impurity of the first conductivity type, directly providing it in the area where the second impurity region is to be formed, and using the conductor pattern as a diffusion source. Examples include a method of thermal diffusion. In the latter method, the conductor pattern can be used as an extraction electrode for the second impurity region of the first conductivity type.
The conductor pattern in the present invention may be formed directly on the semiconductor layer where the second impurity region is located, or may be formed on the first impurity region via an insulating film. The latter conductive pattern can be used as jumper wiring. Examples of such a conductive material include polycrystalline silicon containing impurities of the first conductivity type, or metal silicides containing the impurities such as molybdenum silicide, tungsten silicide, and tantalum silicide.

In the present invention, the following method can be adopted as means for selectively forming an insulating film on the exposed surface of the conductor pattern.

(1) Taking advantage of the fact that the conductor pattern containing impurities of the first conductivity type has a higher oxidation rate than the semiconductor layer, thermal oxidation treatment is performed under appropriate temperature conditions to thickly oxidize the exposed surface of the conductor pattern. A method in which a thin thermal oxide film is grown on an exposed semiconductor layer other than a conductor pattern, and then the thin thermal oxide film is removed to selectively form an insulating film on the exposed surface of the conductor pattern.

(2) After forming a conductor pattern using an insulator pattern as a mask and protruding the pattern like an eave from the conductor pattern, an insulating film having selective etching properties is deposited on the insulator pattern, and a reactive A method of selectively forming an insulating film directly under the eaves of an insulating pattern, that is, on the exposed surface of a conductive pattern, by performing anisotropic etching such as ion etching.

(3) An insulating film is deposited on the entire surface including the conductor pattern, and etched to the thickness of the insulating film using a directional reactive ion etching method to form a layer on the exposed surface (side surface) of the conductor pattern on the plane of the semiconductor substrate. A method that leaves an apparently thick insulating film deposited in a direction perpendicular to the surface.

In the present invention, an oxidation-resistant insulating film is selectively provided on the side surface of the protruding semiconductor region formed after etching.It is used as an oxidation-resistant mask during thermal oxidation, and is selectively oxidized on the exposed bottom surface of the etched portion. This is to prevent the formation of an oxide film on the side surface of the first impurity region in contact with the electrode while growing the film. Examples of such an oxidation-resistant insulating film include a silicon nitride film and an alumina film.

In the present invention, the material for the lead-out electrode of the first impurity region formed after removing the oxidation-resistant insulating film is, for example, Al, Al-Cu, Al-Si, Al-Si.
Examples include Al alloys such as -Cu, metals such as Mo, W, Ta, and Pt, and silicides of these metals. Note that after removing the oxidation-resistant insulating film and before forming the electrode, an impurity having the same conductivity type as the first impurity region may be diffused into the exposed portion other than the insulating film on the side surface of the protruding semiconductor region. If the second conductivity type impurity region is formed in the exposed portion of the side surface of the protruding semiconductor region in this way, when the lead-out electrode for the first impurity region is formed, the first impurity region and the second impurity region are separated by the electrode. It is possible to reliably prevent a short circuit between the first impurity region and the semiconductor layer of the first conductivity type in some cases.

Next, an example in which the present invention is applied to the production of I ² L will be described with reference to FIGS. 3a to 3i.

Example [] First, Sb is selectively diffused into a p-type silicon substrate 101 to form an n+ buried layer 102, and then an n ⁺ buried layer 102 is formed.
After growing the type silicon epitaxial layer 103 (semiconductor layer of the first conductivity type),
A field oxide film 104 was selectively provided around the I ² L gate. Subsequently, a p ^- type base region 105 (second conductivity type first impurity region) of an intrinsic npn transistor was formed in a part of the silicon epitaxial layer 103 by ion implantation or the like. In this case, p ^- type base region 105 may be formed from the surface of n-type silicon epitaxial layer 103 by a diffusion method. Subsequently, thermal oxidation treatment and selective etching were performed to obtain the above-mentioned
A silicon oxide film 106 covering the base region of the pnp transistor and a silicon oxide film 107 covering a part of the p ^- type base region 105 were formed.
In this case, the silicon oxide film 107 for insulating the latter jumper wiring is replaced with the field oxide film 1.
It may be formed thickly in the same process as 04. Thereafter, an n ⁺ type polycrystalline silicon film 108 containing arsenic as an n-type impurity, a CVD-SiO ₂ film 109, and a silicon nitride film 110 were deposited in sequence (third
Figure a).

[] Next, resist patterns (not shown) are formed on the silicon nitride film 110 by photolithography, and the silicon nitride film 110 is etched using these resist patterns as a mask to form silicon nitride film patterns 110a to 110c. , the CVD-SiO ₂ film 109 is patterned using these patterns 110a to 110c as masks to form CVD-SiO ₂ film patterns 109a to 1.
09c was formed. Furthermore, using the silicon chambered film patterns 110a to 110c as a mask,
The n ⁺ type polycrystalline silicon film 108 is HF:HNO ₃ :
Etch using CH ₃ COOH = 1:3:8 etchant or reactive ion etching.
N ⁺ type polycrystalline silicon patterns 108a and 108c (conductor patterns) that are in direct contact with the n type silicon epitaxial layer 103 on the p ^- type base region 105 and whose ends extend onto the field oxide film 104, and silicon oxide An n ⁺ -type polycrystalline silicon pattern 108b (conductor pattern) was formed on the silicon epitaxial layer 103 via the film 107, with both ends extending onto the field oxide film 104 (as shown in FIG. 3B).

[] Next, heat treatment was performed in a low-temperature steam or wet atmosphere at 700 to 900°C. At this time,
n ⁺ type polycrystalline silicon patterns 108a to 10
Since the oxidation rate of 8c is about 4 to 10 times higher than that of the low concentration n-type silicon epitaxial layer 103, a thick thermal oxide film is formed on the exposed peripheral side of the patterns 108a to 108c as shown in FIG. 3c. 111 is a thin thermal oxide film (not shown) on the surface of the n-type silicon epitaxial layer 103.
But it has grown. This heat treatment causes direct contact with the n-type silicon epitaxial layer 103.
n ⁺ type polycrystalline silicon pattern 108a, 10
Arsenic from 8c diffuses into the epitaxial layer 103 and forms the n ⁺ type collector region 1 of the npn transistor.
12a and 112b were formed. By forming these collector regions 112a and 112b, n ⁺
Mold polycrystalline silicon patterns 108a, 108c
functions as a collector lead-out electrode, and the n ⁺ type polycrystalline silicon pattern 108b on the silicon oxide film 107 functions as a jumper wiring. Thereafter, a thin thermal oxide film (not shown) was removed by treatment with ammonium fluoride, for example, and thermal oxide films 111 were left around the n ⁺ type polycrystalline silicon patterns 108a to 108c (as shown in FIG. 3c). ).

[] Next, the n-type silicon epitaxial layer 103 exposed by removing the thin thermal oxide film is formed into a field oxide film 104 and a silicon oxide film 10.
6 and n ⁺ type polycrystalline silicon patterns 108a
Using the thermal oxide film 111 around 108c as a mask, etching was performed by reactive ion etching until the p ^- type base region 105 was penetrated. At this time, as shown in FIG. 3d, a protruding vertical npn transistor 113 with vertical side surfaces
A, 113b, a protrusion 114 consisting of an n-type silicon epitaxial layer 103 and a p ^- type base region 105 were formed. This etching eliminates unnecessary parasitic pn junctions and improves I ² L operation.

[] Next, a silicon nitride film 116 was deposited on the entire surface including the etched portions 115 (as shown in FIG. 3e). Subsequently, etching was performed using a reactive ion etching method for a slightly longer time than the etching time required for the film thickness of the nitride film 116. At this time, the apparent thickness of the silicon nitride film 116 deposited on the side surfaces of the protruding npn transistors 113a, 113b, etc. in the direction perpendicular to the substrate is larger than that on other flat areas. ,
In addition, in the reactive ion etching method, etching progresses only in the direction perpendicular to the substrate 101, so that the silicon nitride film 116 is formed only on the side surfaces of the protruding NPN transistors 113a, 113b, protrusions 114, etc., as shown in FIG. 3F. '... remained, and a part of the bottom surface of the etched portion 115... was exposed. In this case, the following method may be adopted as another method for efficiently leaving the silicon nitride film. That is, in the state shown in Figure 3 d,
By using a directional etching method such as RIE, a protrusion 113a having a vertical or almost vertical side surface,
After forming the silicon side surfaces 113b and 114, the etched portion 115 having the silicon side surface is further etched by approximately 1000 mL using an even etching method.
Perform silicon etching of ~2000Å,
The side surface of the protrusion is formed by the silicon pattern 108a~
Thermal oxide film 111 around 108c is “eaves”
Form it so that it looks like this. In this way, the silicon nitride film 116 deposited in the next step can be
When etching with a directional etching method such as RIE, it is possible to leave a silicon nitride film well on the side surface of the protrusion below this "eaves", and it is also possible to leave a silicon nitride film well on the side surface of the protrusion under this "eaves". Since the side surfaces of the protrusions are etched by the etching method, it is also preferable from the standpoint of removing crystal defects generated by etching such as RIE on the side surfaces. Subsequently, the silicon nitride film pattern 110a~
Using the remaining silicon nitride film 110d and the remaining silicon nitride film 116' as an oxidation-resistant mask, thermal oxidation treatment is performed in a high temperature steam or wet atmosphere to form protruding npn transistors 113a, 113.
A thick silicon oxide layer 117 was grown at the bottom of the etched portion 115, such as between the etching holes 115 and 115 (as shown in FIG. 3g). In the growth of the silicon oxides 117, in order to avoid changing the impurity profile of each impurity region in the formed n-type silicon epitaxial layer 103, a short period of time is used at a relatively low temperature using a method such as high-pressure oxidation. It is preferable to do it for an hour. Continuing, the remaining silicon nitride film 11
6'... and silicon nitride film pattern 110a~
110c was removed with phosphoric acid or the like (as shown in Figure 3g).

[] Next, diffusion of boron or vapor phase diffusion of BN, etc. was performed. At this time, as shown in Figure 3h
P-type emitter region (injector) 118 and collector region 119 of the pnp transistor, and protruding vertical npn transistors 113a and 113b
A p-type region (base contact region) 120 was formed on the side surface of the projection 114. Also, a p ^- type region 12 is formed in a part of the n-type silicon epitaxial layer 103 under the p - type base region 105.
0... extends, but most of the extended portions of these p-type regions 120... are in contact with the silicon oxide bodies 117..., so they cannot form a large parasitic p-n junction.
This has almost no effect on the characteristics of I ² L. Next, an Al film is vacuum-deposited on the entire surface and patterned.
Injector lead-out Al electrode 121 and p connected to mold emitter region (injector) 118
p ^- type base region 10 via type region 120...
I ² L was manufactured by forming a base-extracted Al electrode 122 connected to 5 (as shown in FIG. 3i).

According to the method of the present invention described above, various effects listed below can be exhibited.

Etched portions 115 penetrating the p ^- type base region 105 are formed by one etching process to form protruding vertical pnp transistors 113a, 1.
13b and the etched portion 1
In order to selectively grow silicon oxide 117... on the bottom of 15..., it is possible to eliminate the parasitic p-n junction with respect to the p-n junction between the base and emitter of the pnp transistor, and it is possible to obtain I ² L with improved high-speed operation. .

Silicon oxide to eliminate parasitic pn junctions 11
7 is formed by one-time etching after the formation of the n-type silicon epitaxial layer 103 and selective oxidation using the remaining silicon nitride film 116' as a mask, so that the buried silicon oxide layer is removed as in the conventional method. It is possible to avoid the inconvenience of deteriorating the characteristics of a transistor formed in the vicinity of the transistor.

Unlike the conventional method, there is no need to limit the thickness of the n-type silicon epitaxial layer to the depth of the base region so that the silicon oxide is in contact with the base region of the npn transistor, and the degree of freedom in design can be improved.

n ⁺ type collector region 112 of npn transistor
a and 112b are formed using n ⁺ type polycrystalline silicon patterns 108a and 108c as a diffusion source,
In addition, the silicon oxide 117 is formed at the bottom of the etched portion 115 based on etching using the thermal oxide film 111 around the n ⁺ type polycrystalline silicon patterns 108a, 108c as a mask, so that the polycrystalline silicon pattern 108a ,1
08c and collector regions 112a, 112b
can be formed in self-alignment with the silicon oxide body 117, and as a result, highly integrated I ² L can be obtained.

Protruding vertical npn transistor 113a, 1
After forming 13b, the remaining silicon nitride film 116'
By removing boron and diffusing boron, p-type regions (base contact regions) 120 are formed on the side surfaces of the transistors 113a and 113b.
By forming this, short circuits between the base region 105 and the emitter region (n-type silicon epitaxial layer 103) can be reliably prevented, and short circuits between the base and the collector can also be prevented.

Note that the present invention is not limited to the production of I ² L as in the above embodiments, but is also applicable to vertical npn transistors that operate with the second impurity region of the first conductivity type as an emitter.
The present invention can be similarly applied to the manufacture of integrated circuits having npn transistors with small collector-base junction capacitance from which parasitic collector-base junctions have been eliminated, or multifunctional integrated circuits including I ² L and npn transistors.

As described in detail above, according to the present invention, a silicon oxide layer is formed in a self-aligned manner with respect to the collector region of a vertical NPN transistor without being constrained by deterioration of the crystallinity of the epitaxial layer or the depth of the base region of the vertical NPN transistor. This method has remarkable effects such as the ability to easily and mass-produce bipolar semiconductor devices such as I ² L in which the formation of a parasitic pn junction is prevented.

[Brief explanation of the drawing]

Figures 1 a to c are cross-sectional views showing the manufacturing process of I ² L by a conventional method, Figure 2 is a cross-sectional view of I ² L manufactured by an improved conventional method, and Figures 3 a to i are FIG. 3 is a cross-sectional view showing the manufacturing process of I ² L in an embodiment of the invention. 101...p-type silicon substrate, 102...n ⁺
Buried layer, 103...n-type silicon epitaxial layer (first conductivity type semiconductor layer), 104... field oxide film, 105...p ^- type base region (second
conductivity type first impurity region), 106, 107...
Silicon oxide film, 108a to 108c...n ⁺ type polycrystalline silicon pattern (conductor pattern), 1
11... Thick thermal oxide film, 112a, 112b...
n ⁺ type collector region (second impurity region of first conductivity type), 113a, 113b...protruding vertical npn
Transistor, 116...Silicon nitride film (oxidation-resistant insulating film), 117...Silicon oxide, 12
0...p type region (second conductivity type region), 121,1
22...Al electrode.

Claims (1)

[Claims] 1. After forming a first impurity region of a second conductivity type in the surface layer or a part of the interior of a semiconductor layer of a first conductivity type, a semiconductor layer in or on the first impurity region is formed. forming a second impurity region of the first conductivity type; forming a conductor pattern containing an impurity of the first conductivity type on the semiconductor layer in which at least the second impurity region is located; and exposing the conductor pattern. forming an insulating film on the surface, and using this insulating film as a mask, selectively etching the semiconductor layer to the same depth as the first impurity region to form a vertical or After forming a protruding semiconductor region with nearly vertical side surfaces and selectively forming an oxidation-resistant insulating film on the side surfaces of the protruding semiconductor region, thermal oxidation treatment is performed to remove the exposed bottom surface of the etched portion. a step of forming an oxide film on the oxide film, and removing the oxidation-resistant insulating film,
A second layer is applied to the protruding semiconductor region through its side surface.
1. A method for manufacturing a bipolar semiconductor device, comprising the step of forming an electrode connected to a first impurity region of a conductive type. 2. After removing the oxidation-resistant insulating film, and prior to electrode formation, the side surface of the protruding semiconductor region is doped with a second conductivity type impurity to form a second conductivity type region. A method for manufacturing a bipolar semiconductor device according to item 1. 3. A method of manufacturing a bipolar semiconductor device according to claim 1 or 2, characterized in that the second impurity region of the first conductivity type is used as an emitter or collector of a vertical npn transistor.