JPS57190348A - Manufacture of bipolar semiconductor device - Google Patents
Manufacture of bipolar semiconductor deviceInfo
- Publication number
- JPS57190348A JPS57190348A JP56075185A JP7518581A JPS57190348A JP S57190348 A JPS57190348 A JP S57190348A JP 56075185 A JP56075185 A JP 56075185A JP 7518581 A JP7518581 A JP 7518581A JP S57190348 A JPS57190348 A JP S57190348A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- sides
- sio2
- films
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
Abstract
PURPOSE:To obtain conveniently a bipolar semiconductor device of integrated injection logic (I<2>L), etc., by a method wherein an n<+> type layer is piled up on an n type layer having a p<-> type buried layer, perpendicularly etched grooves are formed reaching the buried layer making a polycrystalline Si layer having the oxidized surface as the mask, SiO2 films are formed selectively on the groove bottoms, and electrodes to come in contact with the p<-> type layer through the sides are equipped. CONSTITUTION:SiO2 films 106, 107 are provided selectively on the n type Si epitaxial layer 103 having the p<-> type buried base layer 105, the n<+> type polycrystalline Si layer 108, an SiO2 film 109 are piled up, and etching is performed to expose the n type layer 103 applying an Si3N4 mask 110. The SiO2 film 109, an n<+> type layer 112 extended from the layer 108 are provided on the sides of the layer 108, and etching 115 is performed perpendicularly penentrating the layer 105. The sides are covered with Si3N4 masks 116', and SiO2 films 117 are formed on the groove bottoms. The masks 116' are removed, B ions are diffused in the sides of the protruding bodies to form p type layers 119, and the electrodes 121, 122 are equipped. By this constitution, the oxide films 117 can be formed by self alignment in the collector layers without restricted by deterioration of crystallinity of the epitaxial layer and depth of the base layer of the vertical type npn element, etc., a parasitic p-n junction is not generated, and the bipolar device of I<2>L, etc., can be formed conveniently.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56075185A JPS57190348A (en) | 1981-05-19 | 1981-05-19 | Manufacture of bipolar semiconductor device |
US06/378,480 US4433470A (en) | 1981-05-19 | 1982-05-14 | Method for manufacturing semiconductor device utilizing selective etching and diffusion |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56075185A JPS57190348A (en) | 1981-05-19 | 1981-05-19 | Manufacture of bipolar semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57190348A true JPS57190348A (en) | 1982-11-22 |
JPS6242395B2 JPS6242395B2 (en) | 1987-09-08 |
Family
ID=13568886
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56075185A Granted JPS57190348A (en) | 1981-05-19 | 1981-05-19 | Manufacture of bipolar semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57190348A (en) |
-
1981
- 1981-05-19 JP JP56075185A patent/JPS57190348A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6242395B2 (en) | 1987-09-08 |
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