JPH05347311A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a shallow junction, by forming an insulating film with which a reverse conductive type base is covered on a conductive type collector formed on one main surface of a semiconductor substrate and selectively growing a conductive type silicon layer in an opening of a candidate emitter region. CONSTITUTION:After an N<+>-type buried layer 2 is formed on a P-type silicon substrate 1, an N-type epitaxial layer 3 is grown. Next, after a field oxide film 4 is formed, an N<+>-type collector pull layer 5 and a base oxide film 6 are formed. Then, after a P-type base layer 7 is formed and an interlayer insulating film 8 is deposited and then a base contact 9b, an emitter contact 9a and a collector contact 9c are opened, a residue 8a other than the base contact 9b is removed. Further, after an N<+>-type silicon layer 12 is selectively grown, the residue 8a is removed and electrodes 13 of the contacts 9a to 9c are formed and an element part is completed. Thus, a shallow junction can be formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a high performance bipolar transistor having an extremely shallow junction.

[0002]

2. Description of the Related Art In recent years, the performance of bipolar transistors has been remarkably improved.

In order to improve the performance, first, the pattern is miniaturized to reduce the base resistance and the parasitic resistance. Secondly, the junction is formed shallow to shorten the carrier transit time. It is necessary. With advances in lithography technology, submicron patterns have been put to practical use. Also Si-MBE
This made it possible to form an extremely shallow base junction.

Next, a conventional NPN transistor will be described in the order of steps with reference to FIG.

After the N ⁺ type buried layer 2 is formed on the P type silicon substrate 1, the N type epitaxial layer 3 is grown. Next, a field oxide film 4 for element isolation is formed by a selective oxidation method, and then a base oxide film 6 is formed and then N ⁺
A mold collector pull-up layer 5 is formed. Next, the P-type base 7 is formed by Si-MBE. Next, after depositing the emitter polysilicon 12a doped with N-type impurities,
N ⁺ type emitter 12b is annealed at 0 to 1100 ° C.
To form.

A self-aligned NPN transistor used in a high-speed digital circuit will be described in the order of steps with reference to FIG.

This is done by depositing P ⁺ type polysilicon 10 and then heat treating it to form a P type base layer 7. Then P
^{After the +} type polysilicon 10 is etched to open the intended emitter region, an interlayer insulating film 11 is formed. Next, an emitter polysilicon 12a doped with an N-type impurity is deposited and then heat-treated to form an N ⁺ -type emitter 12b to complete the element portion.

The emitter polysilicon 12a is an NPN.
Although it has contributed greatly to the speedup of transistors,
In order to make the junction shallower to achieve higher performance in the future, there are the following problems. Impurities heavily doped in the emitter polysilicon are not activated as they are, and the crystallinity of the polysilicon is poor. Therefore, it has to be annealed at high temperature to form an emitter-base junction in the P-type base layer. This high-temperature annealing causes impurities in the P-type base layer to be diffused and redistributed to destroy the profile, so that the emitter-base junction becomes deep and high performance cannot be achieved. The self-aligned transistor shown in FIG. 3B has the following problems. Since the drawer of the base electrode with the P ⁺ -type polysilicon 10, it is necessary to lower the sheet resistance [rho _s of P ⁺ -type polysilicon 10 in order to reduce the base resistance. Therefore, if the P ⁺ type polysilicon 10 is made thick, the aspect ratio (ratio of thickness to width) of the emitter polysilicon 12a becomes large. The supply of impurities to the N ⁺ type emitter 12b is reduced and the carrier injection efficiency is reduced. This becomes a particularly serious problem when the emitter polysilicon 12a is formed by ion-implanting arsenic after depositing polysilicon. When trying to miniaturize the emitter size in order to increase the speed, it becomes an even greater obstacle.

[0009]

The conventional structure using emitter polysilicon requires high temperature annealing for activation. In the self-aligned transistor, the aspect ratio of the emitter polysilicon is further increased and the carrier injection efficiency is lowered. There was a problem in forming such a shallow junction, and it was difficult to achieve high performance.

[0010]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a base of opposite conductivity type on a collector of one conductivity type formed on one main surface of a semiconductor substrate, and the base. After forming an insulating film covering the above, a step of forming an opening in the expected emitter region and a step of selectively growing a silicon layer of one conductivity type only in the opening are included.

[0011]

EXAMPLE FIG. 1A shows a first example of the present invention.
The process order will be described with reference to FIGS.

First, as shown in FIG. 1A, an N ⁺ type buried layer 2 is formed on a P type silicon substrate 1, and then an N type epitaxial layer 3 is grown. Next, after forming a field oxide film 4 for element isolation by selective oxidation,
An N ⁺ type collector pulling layer 5 and a base oxide film 6 are formed.

Next, as shown in FIG. 1 (b), Si-M
According to BE, the impurity concentration is 1 × 10 ^{18 to} 3 × 10 ²⁰ cm ^-3 ,
The P-type base layer 7 having a thickness of 20 to 100 nm is formed.

Here, the P-type base layer 7 can be formed by using a CVD method such as photo CVD, an ion implantation method or a diffusion method instead of Si-MBE. Alternatively, a similar effect can be obtained by forming a heterocrystal such as a SiGe mixed crystal instead of the P-type base layer 7.

Next, after the interlayer insulating film 8 is deposited and the base contact 9b, the emitter contact 9a and the collector contact 9c are opened, the base contact 9 is formed.
The residue 8a other than on b is removed.

Next, as shown in FIG. 1 (c), arsenic (As),
5 × 10 ^{19 of} one of antimony (Sb) and phosphorus (P)
cm ⁻³ to 1 × 10 ²¹ cm ⁻³ Doped thickness 100 to 50
After selectively growing a 0 nm N ⁺ type silicon layer 12,
The residue 8a is removed. The gas used and its flow rate and pressure are optimized to prevent silicon from growing on the residue 8a of the base contact 9b.

Next, as shown in FIG. 1D, a metal electrode 13 having a thickness of 1 μm is formed on the contacts 9a, 9b, 9c to complete the element portion. Aluminum metal (Al, Al-Si, Al-Si-Cu) or multilayer metal (Ti / Pt / Au) can be used as the metal electrode 13.

Next, a self-aligned transistor as a second embodiment of the present invention will be described with reference to FIGS. 2 (a) to 2 (c).

First, as shown in FIG. 2A, an N ⁺ type buried layer 2, an N type epitaxial layer 3, a field oxide film 4, an N ⁺ type collector pulling layer 5, a base oxide film are formed on a P type silicon substrate 1. 6 is formed. The process up to this point is the same as in the first embodiment.

Next, as shown in FIG. 2B, ¹¹ B ⁺ is ion-implanted or BCl ₃ gas is thermally diffused to form P.
The mold base layer 7 is formed. Next, thickness 150-500n
m P ⁺ type polysilicon 10 and thickness 150-300
After the interlayer insulating film 11 having a thickness of 10 nm is formed, the N ⁺ type silicon layer 12 is selectively grown.

Next, as shown in FIG. 2C, a metal electrode 13 having a thickness of 1 μm is formed on the contacts of the emitter, base and collector to complete the element portion.

The above, directly on the N ⁺ -type silicon layer 12 has formed the metal electrodes 13 can sandwich the N ⁺ -type polysilicon between the N ⁺ -type silicon layer 12 and the metal electrode 13. By forming the N ⁺ type polysilicon, the breakdown of the emitter-base junction due to the alloy spike can be prevented.

In addition to the semiconductor integrated circuit, the present invention is applicable to N
It can also be applied to a discrete transistor (individual transistor) by growing an N-type epitaxial layer on a ⁺ type silicon substrate. Further, not only the NPN transistor but also the PNP transistor can be applied by changing the polarity of impurities.

[0024]

The use of the selectively grown N ⁺ type silicon layer as the emitter has the following effects in improving the performance of the bipolar transistor. Activation by heat treatment is no longer necessary, as is the case with polysilicon. Since N ⁺ only N ⁺ -type emitter grown type silicon layer is formed, no redistribution of P-type base layer. A shallow P-type base layer can be maintained. In the self-aligned transistor, the implantation efficiency does not decrease even if the P ⁺ -type polysilicon layer is thickened to increase the aspect ratio in order to reduce the base resistance.

[Brief description of drawings]

1A to 1C are cross-sectional views showing a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a second embodiment of the present invention in process order.

FIG. 3 is a sectional view showing a conventional NPN transistor.

[Explanation of symbols]

1 P-type silicon substrate 2 N ⁺ type buried layer 3 N type epitaxial layer 4 Field oxide film 5 N ⁺ type collector pull-up layer 6 Base oxide film 7 P type base layer 8 Interlayer insulating film 8a Residue 9a Emitter contact 9b Base contact 9c Collector contact 10 P ⁺ type polysilicon 11 Interlayer insulating film 12 N ⁺ type silicon layer 12a Emitter polysilicon 12b N ⁺ type emitter 13 Metal electrode

Claims (1)

[Claims] 1. A step of forming a base of opposite conductivity type on a collector of one conductivity type formed on one main surface of a semiconductor substrate, and an insulating film covering the base, and then forming an opening in an intended emitter region. And a step of selectively growing a silicon layer of one conductivity type only in the opening.