JP2629162B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a bipolar transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art As the speed of LSIs increases, the speed of bipolar transistors must be further increased.
Generally, in order to increase the speed of a bipolar transistor, it is necessary to reduce the parasitic capacitance. The self-alignment of the base and the emitter has reduced the element size and reduced the parasitic capacitance. However, as the element becomes finer, the distance between the emitter region and the external base region becomes shorter, causing a problem of a reduction in the emitter-base reverse breakdown voltage. Therefore, a technique for reducing the parasitic capacitance without lowering the reverse breakdown voltage between the emitter and the base has been required.

A method for manufacturing a conventional self-aligned bipolar transistor will be described with reference to FIGS.

First, the surface of the n-type epitaxial layer 1 is thermally oxidized to form a silicon oxide film 2 having a thickness of 0.04 to 0.06 μm. Next, a polycrystalline silicon film 3 having a thickness of 0.2 to 0.25 μm is deposited by a CVD method, and boron as a p-type impurity is ion-implanted. Then 0.2-0.3μ in thickness
3A is deposited by CVD, and the silicon oxide film 4 and the polycrystalline silicon film 3 at the portions where the base region and the emitter region of the bipolar transistor are to be formed are removed by anisotropic etching. Then, the emitter portion is opened to expose the silicon oxide film 2 as shown in FIG.

Next, the exposed portion of the silicon oxide film 2 and the lower portion of the polycrystalline silicon film 3 are removed by etching with dilute hydrofluoric acid to form an undercut portion having a width of about 0.1 μm.
Next, a thickness of 0.0
CVD of polycrystalline silicon film 11 of about 3 to 0.06 μm
After the deposition by the method, the polycrystalline silicon film 11 is etched to leave the polycrystalline silicon 11 in the undercut portion as shown in FIG.

Next, boron is applied to the opening,
After ion implantation at 0 KeV dose of 2 × 10 ¹³ cm ⁻² and heat treatment at 900 ° C. for 20 minutes to form a base region 6 as shown in FIG. Thus, the insulating film 7 is deposited, and the insulating film 7 other than the side wall of the opening is removed by anisotropic etching. Next, an n-type polycrystalline silicon film 8 is deposited and patterned, and then a heat treatment is performed to diffuse impurities in the n-type polycrystalline silicon into the base region 6 to form an emitter region 9. The external base region 10 is formed by forming the n-type epitaxial layer from the polycrystalline silicon film 3 through the polycrystalline silicon 11 by the heat treatment after the polycrystalline silicon 11 is formed (mainly, the heat treatment after the ion implantation for forming the base region 6). 1 to form an external base region 10 as shown in FIG. All of the polycrystalline silicon films used in this conventional manufacturing technique are polycrystalline silicon having an average crystal grain size of 0.2 μm or less.

[0007]

In the conventional manufacturing method, since the external base region 10 is expanded mainly by the heat treatment at 900 ° C. for 20 minutes for forming the base region 6, the expansion of the external base region 10 can be suppressed. If the distance between the base and the emitter is reduced to reduce the parasitic capacitance, the reverse breakdown voltage of the base and the emitter is reduced. In order to secure the reverse withstand voltage, the silicon oxide film 7 is made thick to form the external base region 10.
When the distance between the emitter region and the emitter region 9 is increased, the problem is that if the emitter size is the same, the parasitic capacitance increases or the base resistance increases.

Means for solving such a problem is 5-24.
3246 and JP-A-5-36706.

Japanese Patent Application Laid-Open No. 5-243 shown in FIGS.
No. 246, an n ⁺ -type buried layer 12 and a p ⁺ -type buried layer 15 are first formed on a p-type silicon substrate 14, and then n
The type epitaxial layer 1 is grown, and a silicon oxide film 13 for element isolation is formed as shown in FIG.

Next, after a silicon nitride film 17 and a silicon oxide film (not shown) are sequentially deposited, the silicon nitride film 17 is removed by etching while leaving an emitter formation region. Thereafter, polycrystalline silicon 16 for the base electrode is deposited on the entire surface, flattened with a photoresist, etched back to expose the surface of the silicon oxide film, and the silicon oxide film is removed with buffered hydrofluoric acid. Thereafter, boron is ion-implanted at a dose of about 1E13 cm ^{-2 at} 30 keV and thermally diffused to form a low-concentration external base region 18. Further, boron is ion-implanted at a dose of about 1E15 cm ^{-2 at} 30 keV to form a high-concentration external base region 10.
Is formed [FIG. 5 (b)].

Next, the surface of the polycrystalline silicon 16 is oxidized and etched so that the silicon oxide film 19 and the silicon nitride film 17 are left on the surface and side surfaces [FIG. 6 (a)].

Next, an intrinsic base region 6 is formed by ion implantation, polycrystalline silicon 8 is further deposited, and arsenic is ion-implanted and thermally diffused to form an emitter region 9 (FIG. 6B).

[0013] Further, Japanese Patent Laid-Open No. 5-36706 shown in FIG.
In the description, the polycrystalline silicon film 3 is formed on the n-type epitaxial layer 1.
After boron is ion-implanted, a silicon oxide film 4 is deposited. Next, a base and emitter formation region is opened, and a silicon oxide film (BS
G film) 20 and then anisotropic etching
The SG film 20 is left only on the side of the opening. Then, ions are implanted into the opening to form an intrinsic base region. Next, after a non-doped silicon oxide film is grown on the entire surface and anisotropically etched, a polycrystalline silicon film 8 is deposited, and arsenic is ion-implanted and thermally diffused to form an emitter region 9.

In the known examples shown in FIGS. 5 to 7, the reduction of the base-emitter reverse breakdown voltage is prevented by lowering the boron concentration at the junction between the emitter region and the base region. However, the thermal diffusion of boron from the polycrystalline silicon into the n-type epitaxial layer cannot be suppressed, and the high-concentration external base region expands, which causes a problem of an increase in parasitic capacitance. Therefore, in order to suppress the extension of the external base region, it is necessary to diffuse boron through a conductive material that diffuses slowly.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a bipolar transistor having a small base-emitter parasitic capacitance and a suppressed decrease in the base-emitter reverse breakdown voltage, and a method of manufacturing the same. And

[0016]

According to the present invention, a first insulating film, a second conductive first semiconductor film and a second conductive film are formed on a first conductive type semiconductor region. Forming an insulating film in order, forming an opening in an element forming portion of the second insulating film and the first semiconductor film to expose the first insulating film, and forming the first insulating film. Forming an undercut portion by etching the exposed portion and the lower portion of the first semiconductor film; and forming a polycrystalline silicon film having an average grain size of 0.3 μm or more burying the undercut portion, Etching the polycrystalline silicon film while leaving a portion buried in the undercut portion; and introducing a second conductivity type impurity into the first semiconductor region in a portion exposed by the opening to form a second conductive film. Forming the second semiconductor region of the mold When, it is characterized by a step of forming a third semiconductor region of the second conductivity type surrounding the second semiconductor region with an impurity is thermally diffused from the first semiconductor film.

[0017]

In general, when boron diffuses in polycrystalline silicon, it is known that the speed of diffusion in crystal grain boundaries is faster than the speed of diffusion in silicon crystals. Therefore, in the external base region 10, boron in the polycrystalline silicon film 3 diffuses into the n-type epitaxial layer 1 around the interface between the grain boundary of the polycrystalline silicon film 11 and the epitaxial layer. On the other hand, the reverse breakdown voltage of the bipolar transistor is determined by the distance from the base-emitter junction to the high-concentration external base region and the facing length. Here, in the case of polycrystalline silicon having a small grain boundary as in the conventional example, the spacing between the interfaces is shorter than the diffusion length of boron in the epitaxial layer, so that the boron concentration becomes the sum of boron diffused from the adjacent interface and the high concentration region. The extent of spread becomes large. Therefore, the distance between the emitter and the external base region is shortened, and the reverse breakdown voltage is reduced. When the density of the grain boundaries is high, the ratio of the portion where the distance between the base-emitter junction and the external base region is short becomes high, and the reverse breakdown voltage is reduced.

On the other hand, in the present invention, the density of the grain boundaries of the polycrystalline silicon film is reduced to suppress the diffusion of boron. This eliminates the influence of the adjacent interface, suppresses the spread of the high-concentration region, increases the distance between the base-emitter junction and the external base region, and prevents a reduction in reverse breakdown voltage. When the average grain size of the polycrystalline silicon is 0.3 μm or more, the effect of the present invention can be obtained because the influence of the adjacent interface is eliminated. Therefore, the ratio of the portion where the distance between the base-emitter junction and the external base region is long in the facing length between the base-emitter junction and the external base region is increased, so that a higher effect is obtained.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

First, referring to FIG. 1A, the surface of the n-type epitaxial layer 1 is thermally oxidized to have a thickness of 0.04-0.
A silicon oxide film 2 of 06 μm is formed. Next, the thickness 0.
A polycrystalline silicon film 3 of 2 to 0.25 μm is deposited by a CVD method, and boron as a p-type impurity is ion-implanted over the entire surface. Thereafter, a silicon oxide film 4 having a thickness of 0.2 to 0.3 μm
Is deposited by the CVD method, the silicon oxide film 4 and the polycrystalline silicon film 3 at the portions where the base region and the emitter region of the bipolar transistor are to be formed are removed by anisotropic etching, and the emitter opening as shown in FIG. To expose the silicon oxide film 2. Next, the exposed portion of the silicon oxide film 2 and the portion under the end of the polycrystalline silicon film 3 are removed by etching with dilute hydrofluoric acid to form an undercut portion having a width of about 0.1 μm. Then, an amorphous silicon film having a thickness of at least half the thickness of the silicon oxide film 2 is deposited by a CVD method so as to fill the undercut portion, and a heat treatment at about 600 ° C. is performed in a nitrogen atmosphere to form an amorphous silicon film. The crystalline silicon film is changed to a polycrystalline silicon film 5 having an average particle size of 0.5 μm or more. Next, the polycrystalline silicon film 5 is etched to leave the polycrystalline silicon film 5 in the undercut portion as shown in FIG.

Next, boron is ion-implanted into the opening at, for example, an energy of 10 KeV and a dose of 2 × 10 ¹³ cm ^-2 , and then an appropriate heat treatment is applied to activate the boron.
An intrinsic base region 6 is formed as shown in FIG. By this heat treatment, boron is diffused from the polycrystalline silicon film 3 into the n-type epitaxial layer 1 through the polycrystalline silicon 5 so that the external base region 10 can be formed over the entire interface with the polycrystalline silicon 5. The thickness of the film 2 is adjusted. After the insulating film 7 is further deposited, the insulating film 7 other than the side wall of the opening is removed by anisotropic etching. Finally, an n-type polycrystalline silicon film 8 is deposited and patterned, and then subjected to a heat treatment to diffuse the impurities of the n-type polycrystalline silicon 8 into the intrinsic base region 6 to form an emitter region 9 (FIG. 2B).

As a second embodiment of the present invention, an undercut portion is formed in the same manner as in the first embodiment, and then polycrystalline by a CVD method using disilane at a temperature of 770 ° C. instead of polycrystalline silicon 5. Grow silicon. Thereafter, a base region and an emitter region are formed in the same manner as in the first embodiment.
The other structures and manufacturing steps are the same as those of the first embodiment, and the description is omitted.

[0023]

According to the present invention, polycrystalline silicon in which boron is diffused to form an external base region has a smaller average particle diameter than conventional polycrystalline silicon having an average particle diameter of 0.2 μm or less. By using polycrystalline silicon having a diameter of 0.2 μm or more, the extension of the external base region can be suppressed, and the parasitic capacitance can be reduced without lowering the base-emitter reverse breakdown voltage. In the second embodiment, the polycrystalline silicon is used as the polycrystalline silicon 5 in the first embodiment, thereby eliminating grain boundaries and further suppressing the diffusion of boron. Therefore, the base parasitic capacitance can be reduced without lowering the base-emitter reverse breakdown voltage.

[Brief description of the drawings]

1 (a) and 1 (b) are cross-sectional views of an embodiment of the present invention in the order of manufacturing steps.

FIGS. 2A and 2B are cross-sectional views in the order of the manufacturing process of one embodiment of the present invention following FIGS. 1A and 1B.

3A and 3B are cross-sectional views of an example of a conventional semiconductor device in the order of manufacturing steps.

FIGS. 4A and 4B are cross-sectional views of an example of a conventional semiconductor device following FIGS. 3A and 3B in the order of manufacturing steps.

5A and 5B are cross-sectional views of another example of a conventional semiconductor device in the order of manufacturing steps.

FIGS. 6A and 6B are cross-sectional views of another example of the conventional semiconductor device following FIGS. 5A and 5B in the order of manufacturing steps.

FIG. 7 is a sectional view of still another example of a conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 1 n-type epitaxial layer 2 silicon oxide film 3 p ⁺ polycrystalline silicon film 4 silicon oxide film 5 polycrystalline silicon film 6 intrinsic base region 7 silicon oxide film 8 n ⁺ type polycrystalline silicon film 9 emitter region 10 external base region 11 multi Crystalline silicon film 12 n ⁺ type buried layer 13 silicon oxide film 14 p-type silicon substrate 15 p ⁺ type buried layer 16 n ⁺ type polycrystalline silicon film 17 silicon nitride film 18 low concentration external base region 19 silicon oxide film

Claims (4)

(57) [Claims] A first semiconductor region of a first conductivity type;
Forming an insulating film, a first semiconductor film of a second conductivity type, and a second insulating film in this order; and forming an opening in an element forming portion of the second insulating film and the first semiconductor film. Exposing the first insulating film, etching an exposed portion of the first insulating film and a lower portion of the first semiconductor film to form an undercut portion, and embedding the undercut portion in an average. Forming a polycrystalline silicon film having a grain size of 0.3 μm or more, and introducing a second conductivity type impurity into a portion of the first semiconductor region exposed by the opening.
Forming a second semiconductor region of a conductivity type;
Forming a third semiconductor region of the second conductivity type around the second semiconductor region by thermally diffusing impurities from the semiconductor film. 2. The method according to claim 1, wherein the first semiconductor film of the second conductivity type is polycrystalline silicon having an average grain size of 0.3 μm or more. 3. The semiconductor device according to claim 1, wherein said polycrystalline silicon film having an average grain size of 0.3 μm or more is formed by subjecting an amorphous silicon film to a heat treatment in a nitrogen atmosphere. Manufacturing method. 4. A semiconductor substrate in which an emitter region, a base region, a collector region, and a high-concentration external base region for electrically connecting the base electrode and the base region are formed, and a base electrode for forming a base electrode. A semiconductor device having a polycrystalline silicon layer, wherein at least a contact portion of the polycrystalline silicon layer with the external base region is polycrystalline silicon having an average grain size of 0.3 μm or more.