JPH073870B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a semiconductor integrated circuit device, and more particularly to a method for manufacturing a semiconductor integrated circuit device including a bipolar transistor or a Schottky diode.

[Conventional technology]

Generally, in a semiconductor integrated circuit having a buried high concentration region in a semiconductor substrate such as a bipolar transistor and a Schottky diode, a structure shown in FIG. 4 is taken as a contact structure for the buried high concentration region. In FIG. 4, a field insulating film 64 is formed on the semiconductor substrate 61 by a selective oxidation method, and a buried high-concentration second semiconductor region 62 and a third semiconductor region 63 are formed in the defined element formation region 66.
The element is formed here. Further, a high-concentration fourth semiconductor region having the same conductivity type as the buried high-concentration second semiconductor region 62 is formed by impurity diffusion and drive-in in the contact region 67 adjacent thereto.
65 is formed, and the contact to the buried high-concentration second semiconductor region 62 is taken out.

[Problems to be solved by the invention]

In the above-mentioned conventional technique, particularly in the contact structure, the resistance component of the fourth semiconductor region 65 exists, so that there is a limit in increasing the operating speed of the device. In particular, the presence of this resistor increases the collector series resistance of the bipolar transistor and the series resistance of the Schottky diode, which impedes the speedup of the device.

In addition, in an element requiring a high breakdown voltage, the third semiconductor region 63
Is thick, the buried high-concentration second semiconductor region 62 has a high-concentration fourth
A heat treatment at high temperature for a long time is required to connect the semiconductor regions 65. As a result, there is a problem in that the characteristics of the element formed in the element formation region 66 deteriorate due to the upward diffusion of the impurities in the buried high-concentration second semiconductor region 62.

It is an object of the present invention to provide a method for manufacturing a semiconductor integrated circuit device having low contact resistance and requiring no heat treatment step.

[Means for solving problems]

A method of manufacturing a semiconductor integrated circuit device according to the present invention comprises a step of forming a second semiconductor region containing a high concentration of impurities on a semiconductor substrate as a first semiconductor, and a step of selectively forming a part of the second semiconductor region. A step of forming an insulating film on the second semiconductor region, a step of growing a third semiconductor on the second semiconductor region by a silicon growth method to form a third semiconductor region, and a step of forming a third semiconductor on the insulating film. A step of sequentially removing the crystalline silicon portion and the insulating film by etching to form a concave portion exposing the second semiconductor region, and a second semiconductor region and an ohmic characteristic on the second semiconductor region exposed in the concave portion. And a step of forming a contact electrode made of the metal silicide.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1 (a) to 1 (d) are sectional views showing an embodiment of the manufacturing method of the present invention in the order of steps.

Here, as shown in FIG. 1 (a), the impurity concentration is 10 ¹⁴ to 10
Impurity concentration of 10 ¹⁸ to 10 ²⁰ on the ¹⁵ cm ⁻³ p-type silicon substrate 1
After selectively providing an n-type high concentration region 2 of cm ⁻³ , a thermal oxide film of about 0.1 μm is formed by overall surface oxidation. Thereafter, the thermal oxide film 3 is left only on the contact region 7 and the others are removed.

Next, as shown in FIG. 3B, n-type silicon 4 having an impurity concentration of 10 ¹⁵ to 10 ¹⁷ cm ⁻³ is deposited on the p-type silicon substrate 1 by about 2 μm.
Grow. At this time, polycrystalline silicon 5 is grown on the thermal oxide film 3, and single crystal silicon is epitaxially grown on the other regions.

After that, a field oxide film 6 is formed to define a contact region 7 and an element forming region 8 as shown in FIG. Then, the polycrystalline silicon 5 is removed by dry or wet etching by utilizing the etching selection ratio of the polycrystalline silicon and the single crystal silicon, and the thermal oxide film 3 is also removed by dry or wet etching.

As a result, as shown in FIG. 3D, a recess is formed in the portion where the polycrystalline silicon 5 and the thermal oxide film 3 were present, and the n-type high concentration region 2 is exposed at the bottom of this recess.

After that, a contact structure can be formed by forming an electrode metal or the like in the recess, and the contact electrode metal is in direct contact with the n-type high concentration region 2 and another high concentration semiconductor region is interposed therebetween. There is no. The method of forming the contact electrode will be described together with the description of the structure example of the transistor described below.

FIG. 2 is a Bi-CMOS manufactured by the method shown in FIG.
FIG. 3 is a cross-sectional view of an example of a (bipolar complementary MOS) integrated circuit device.

That is, the n-type high-concentration buried region 12, p is formed on the p-type silicon substrate 11.
A high-concentration type buried region 13 is formed, and n-type silicon 14 is further grown thereon. At the time of growing the n-type silicon 14, the process shown in FIG. 1 is adopted in the collector extraction region 31 of the npn bipolar transistor formation region 30 to form a contact recess. That is, the entire surface is thermally oxidized before the growth of the n-type silicon 14, the oxide film other than the collector extraction region 31 on the n-type high-concentration buried region 12 is removed, and then the n-type silicon 14 is grown. After the formation of the well region 15 and the p-type well region 16 and element isolation by the field oxide film 17, the polycrystalline silicon grown on the oxide film in the collector extraction region 31 and the oxide film are etched to form the contact recess. To form.

Then, on the p-channel MOSFET formation region 28, a p-type source
Drain region 19 and gate electrode 22 are formed to form a p-channel
N-channel MOSFET formation region region 29 that constitutes a MOSFET
An n-type source / drain region 20 and a gate electrode 22 are formed thereon to form an n-channel MOSFET, and a base region 18, an n-type emitter region 21 and an emitter polycrystalline silicon 24 are further formed on an npn bipolar transistor forming region 30. To form a bipolar transistor.

Then, the Pt silicide layer 25 having a thickness of 30 nm to 100 nm and the reaction between the Pt silicide layer and aluminum are prevented in the contact holes formed in the gate oxide film 27 and the interlayer insulating film 23 including the inside of the contact recess. A TiW film with a thickness of about 100 nm, which is a barrier metal for doing so (not shown in the figure)
And an aluminum layer 26 having a thickness of 500 to 1000 nm is formed thereon to form an element contact. In particular,
After forming the contact hole, Pt having a thickness of about 30 nm is deposited on the entire surface and heat treatment is performed at 500 ° C. for about 20 minutes. At this time,
Only Pt on silicon reacts with silicon to form Pt silicidation. After removing unreacted Pt with aqua regia, thickness
A TiW layer having a thickness of about 100 nm and an aluminum layer 26 having a thickness of 1 μm to be an electrode are deposited and patterned. It should be noted that, as in this embodiment, an n-type impurity containing 10 ¹⁹ cm ⁻³ or more is contained.
The junction between the high-concentration type buried region 12 and the Pt silicide layer 25 exhibits good ohmic characteristics with low contact resistance.

Therefore, according to this structure, in the collector take-out region 31 of the npn bipolar transistor, the electrode made of the silicide layer 25 and the aluminum layer 26 is brought into direct contact with the n-type high-concentration buried region 12 to make contact. It is possible to significantly reduce the collector resistance of the npn bipolar transistor. Further, when forming this contact, heat treatment for reaching the contact high-concentration region to the n-type high-concentration buried region 12 is unnecessary, so that n
It is possible to suppress upward diffusion of impurities from the high-concentration type buried region 12 and the p-type high-concentration buried region 13.

FIG. 3 is a sectional view of an embodiment in which a Schottky diode is manufactured by using the method shown in FIG.

That is, the n-type high-concentration buried region 42 is formed on the p-type silicon substrate 41, and the n-type silicon region 43 is formed thereon. When the n-type silicon region 43 is formed, the step shown in FIG. 1 is adopted to form a contact recess with the n-type high-concentration buried region 42 in the contact region 51. At this time, forming the recess after forming the field oxide film 45 is the same as in the example of FIG.

Then, after forming the p-type high concentration region 44 in the diode region 50, the interlayer insulating film 46 is opened, and the platinum silicide 47 and the TiW layer are formed.
A Schottky diode is formed by forming 48 and an aluminum layer 49. At this time, the layers 47, 48, 49 are similarly formed in the recesses of the contact region 51 to complete the contact region 51.

Also in the present embodiment, in the contact region 51, the contact electrode can be brought into direct contact with the n-type high-concentration buried region 42, so that the contact resistance is reduced and the impurity is diffused upward in each region as in the case of the above-described embodiment. The effect of preventing

〔The invention's effect〕

According to the manufacturing method of the present invention, an insulating film is selectively formed on a portion of the second semiconductor region containing a high concentration of impurities, and then the third semiconductor region is grown, and then the third semiconductor region is formed on the insulating film. Since the third semiconductor region and this insulating film are removed by etching to form the recess and the contact electrode made of metal silicide is formed, the number of steps can be increased without significantly changing the conventional manufacturing steps. It is possible to manufacture bipolar transistors with low collector resistance and Schottky diodes with low series resistance.

[Brief description of drawings]

1 (a) to 1 (d) are sectional views showing the manufacturing method of the present invention in the order of steps, FIG. 2 is a sectional view of an embodiment of the present invention, and FIG. 3 is another embodiment of the present invention. FIG. 4 is a sectional view showing an example, and FIG. 4 is a sectional view showing an example of a conventional structure. DESCRIPTION OF SYMBOLS 1 ... P-type silicon substrate, 2 ... n-type high concentration area | region, 3 ... thermal oxide film, 4 ... n-type silicon, 5 ... polycrystalline silicon, 6 ... field oxide film, 7 ... contact area, 8 ... element formation area, 11 ... p-type silicon substrate, 12 ... n-type high-concentration buried region,
13 ... P-type high-concentration buried region, 14 ... N-type silicon region, 15 ...
n-type well region, 16 ... P-type well region, 17 ... field oxide film, 18 ... base region, 19 ... p region, 20 ... n region, 21
... n-type emitter region, 22 ... gate electrode, 23 ... interlayer insulating film, 24 ... emitter polycrystalline silicon, 25 ... TiW / Pt silicide, 26 ... aluminum, 27 ... gate oxide film, 28 ... p-channel MOSFET formation region, 29 ... n-channel MOSFET formation region,
30 ... Npn bipolar transistor formation region, 31 ... Collector extraction region, 41 ... P-type silicon substrate, 42 ... N-type high-concentration buried region, 43 ... N-type silicon region, 44 ... P-region, 45 ...
Field oxide film, 46 ... Interlayer insulating film, 47 ... Platinum silicide, 48 ... TiW, 49 ... Aluminum, 50 ... Diode region, 51 ... Contact region, 61 ... Semiconductor substrate, 62 ... Buried high concentration second semiconductor region, 63 ... third semiconductor region, 64 ... field insulating film, 65 ... high-concentration fourth semiconductor region, 66 ... element forming region, 67 ... contact region.

Claims (1)

[Claims] 1. A step of forming a second semiconductor region containing a high concentration of impurities on a semiconductor substrate as a first semiconductor, and a step of selectively forming an insulating film on a part of the second semiconductor region. A step of growing a third semiconductor on the second semiconductor region by a silicon growth method to form a third semiconductor region, and a polycrystalline silicon portion of the third semiconductor formed on the insulating film and an insulating film. Are sequentially removed by etching to remove the second
A step of forming a concave portion exposing the semiconductor region, and a step of forming a contact electrode made of a metal silicide having ohmic characteristics with the second semiconductor region on the second semiconductor region exposed in the concave portion. A method of manufacturing a semiconductor integrated circuit device having a feature.