JPS58216453A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS58216453A JPS58216453A JP9947082A JP9947082A JPS58216453A JP S58216453 A JPS58216453 A JP S58216453A JP 9947082 A JP9947082 A JP 9947082A JP 9947082 A JP9947082 A JP 9947082A JP S58216453 A JPS58216453 A JP S58216453A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- thick
- approx
- diffused layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 7
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000009792 diffusion process Methods 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 6
- 238000000407 epitaxy Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 229910052681 coesite Inorganic materials 0.000 abstract description 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 4
- 229910052682 stishovite Inorganic materials 0.000 abstract description 4
- 229910052905 tridymite Inorganic materials 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 （ａｌ 発明の技術分野 本発明は半導体装置、特に抵抗素子に関する。[Detailed description of the invention] (al Technical field of invention The present invention relates to semiconductor devices, and particularly to resistive elements.
（ｂｌ 従来技術と問題点
半導体集積回路（ＩＣ）においては、トランジスタ素子
と共に多数の抵抗素子が設けられるが、工Ｃの低電力化
のために最近これらの抵抗素子は抵抗値が数にΩないし
は数１０に４Ａと高抵抗となっており、それは例えば硼
素のイオン注入法で作成されて、シート抵抗がＩＫＩＪ
／口稈度のものである。(bl) Prior Art and Problems In semiconductor integrated circuits (ICs), a large number of resistance elements are provided along with transistor elements, but recently, in order to reduce the power consumption of engineering circuits, these resistance elements have a resistance value of several Ω or more. It has a high resistance of 4A in several 10s, and is created by, for example, boron ion implantation, and the sheet resistance is IKIJ.
/ It is of oral culm size.
しかしながら、すべてを高抵抗素子というわけではなく
、出力バッファ抵抗などは数１００Ω／口程度の抵抗値
を必要として、その場合に１記の高いシート抵抗体で形
成すれば、精度が萼くまたパターンが大きくなるから、
シート抵抗が２０Ω／口程度である埋没拡散層が利用さ
れて、このような低抵抗素子が少数個ＩＣ内に含まれる
。However, not all elements are high resistance elements, such as output buffer resistors, which require a resistance value of several hundred ohms per unit. Because it becomes larger,
A buried diffusion layer with a sheet resistance on the order of 20 Ω/hole is utilized to include a small number of such low resistance elements within the IC.
このような埋没拡散層からなる抵抗素子の断面構造図を
第１図に示しており、ｌはＰ型シリコン晶板、２はｎ
型埋没拡散層、３は厚いフィールド二酸化Ｖリコン（Ｓ
ｉ−０ｇ ）ｆｉｌ、４はｎａエピタキシャル層、５は
電極コンタクト層、６は電極、７は薄い５ｉ０２膜であ
る。しかし、この抵抗素子の構造は埋没拡散層２と電極
コンタクト層６との間にエピタキシャル層のＡ部分が介
在して、エピタキシャル層は比抵抗０．６に１−ａｘ程
度であるから、このＡ部分の抵抗分が曲部分と比べて非
常に高くなる。したがって、その距離の備かの変動も抵
抗値に大きなバラツキを生ずる悪影響がある。A cross-sectional structural diagram of a resistor element consisting of such a buried diffusion layer is shown in FIG.
Type buried diffusion layer, 3 is thick field silicon dioxide V silicon (S
i-0g) fil, 4 is a na epitaxial layer, 5 is an electrode contact layer, 6 is an electrode, and 7 is a thin 5i02 film. However, in the structure of this resistance element, part A of the epitaxial layer is interposed between the buried diffusion layer 2 and the electrode contact layer 6, and the epitaxial layer has a specific resistance of about 1-ax at 0.6. The resistance of this part is much higher than that of the curved part. Therefore, variations in the distance also have the negative effect of causing large variations in resistance values.
今、例えば’ｒ［Ｉ至６の広さを８μｍ×４１１ｍとし
、Ａ部分の距離を０５μｍ、エピタキシャル層の比抵抗
Ｘ０．５＝７８” にも達する。実際にはＡ部分の距
離を史に縮めるため、２００Ｑの抵抗素子形成もｉｉＪ
能となるが、その影響の大きいことはこれより明白であ
る。Now, for example, if the width of 'r [I to 6 is 8 μm x 411 m, the distance of part A is 05 μm, and the specific resistance of the epitaxial layer X0.5 = 78''.In reality, the distance of part A is In order to reduce the size, 200Q resistance element formation is also required.
However, it is clear that the impact is significant.
したがって、曲の方法として埋没拡散層２と直接接続す
るための深い゛Ｍｔｆｉｔコンタクト層を形成する方法
が考えられるが、それだけ余分の工程を要することにな
る。上記の？［Ｍコンタクト−５の場合は、エミッタ拡
散層と同時に形成されるだめ、工程の増加とはならない
。Therefore, one possible method would be to form a deep Mtfit contact layer for direct connection to the buried diffusion layer 2, but this would require an extra process. above? [In the case of M contact-5, the number of steps is not increased because it is formed at the same time as the emitter diffusion layer.
ｔｃ＋ 発明の目的
本発明は上記のような、工程の増加なくして埋没拡散層
を用いた低抵抗素子の抵抗１直のバラツキを解消させる
構造を提案するものである。tc+ OBJECTS OF THE INVENTION The present invention proposes a structure that eliminates the variation in resistance of a low resistance element using a buried diffusion layer without increasing the number of steps as described above.
（■ 発明の構成
その特徴は、半導体基板北に埋没拡散層を形成し、エピ
タキシャル層を成長し、次いで埋没拡散層上面に及ぶ厚
いフィールド５ｉｎＱ膜を形成して成る基体に対し、そ
の厚いフィールド５ｉｎ２膜を窓あけして、埋没拡散層
に直接接続する抵抗素子電極を形成して成る抵抗素子構
造であり、以下図面を参照して詳細に説明する。(■ Structure of the invention The feature is that a buried diffusion layer is formed on the north side of the semiconductor substrate, an epitaxial layer is grown, and then a thick field 5inQ film is formed over the top surface of the buried diffusion layer. This is a resistive element structure in which a window is opened in a film to form a resistive element electrode directly connected to a buried diffusion layer, and will be described in detail below with reference to the drawings.
＋ｅ） 発明の実施例
第２図ないし第４図に本発明にが＼る形成工程順断面図
を示す。第２図に示すように、公知の製法によってＰ型
シリコン基板１土に、高湿度でアンチモニーを拡散して
ｎ 型埋没拡散層２を形成した後、その北面に膜厚１μ
ｍ前後のｎ型エピタキシャル層４を成長する。この時、
図示のように埋没拡散層２はエピタキシャル−４にまで
這い上りの拡散が起る。+e) Embodiment of the Invention Figures 2 to 4 are sectional views showing the steps of the forming process according to the present invention. As shown in FIG. 2, an n-type buried diffusion layer 2 is formed by diffusing antimony into a P-type silicon substrate 1 soil at high humidity using a known manufacturing method, and then a film thickness of 1 μm is formed on the north surface of the n-type buried diffusion layer 2.
An n-type epitaxial layer 4 of approximately m thickness is grown. At this time,
As shown in the figure, diffusion occurs in the buried diffusion layer 2 up to the epitaxial layer 4.
次いで、第３図に示すように同じく公知の製法を用いて
窒化シリコン膜（図示せず）をマスクとして、高温酸化
し膜厚１μｍ程度の厚いフィール １ド
５ｉ０２ 嘆１ Ｂを形成して（素子間分離領域となる
）、次に素子領域上にも膜厚２００ｏ人位の薄いＳｉ、
Ｏ１Ｉ膜７を形成する。この場合、厚いフィールドＳｉ
、０２膜１Ｂは図示のように埋没拡散層２の１面まで達
するように広く形成する。Next, as shown in FIG. 3, using the same well-known manufacturing method and using a silicon nitride film (not shown) as a mask, high-temperature oxidation is performed to form a thick field film with a film thickness of about 1 μm (device ), and then a thin Si film with a thickness of about 200 µm is also deposited on the element area.
An O1I film 7 is formed. In this case, thick field Si
, 02 film 1B is formed wide enough to reach one surface of buried diffusion layer 2 as shown in the figure.
次いで、第４図に示すように、フォトレジスト幌１０を
マスクとして、厚いフーｆ−ルＦ’ ５ＬＯＢ嘆１８を
弗酸溶液でエツチングして窓あけする。膜１享１μｍの
厚い５１０２膜であるが、弗酸によってＳｉｎ、はエツ
チングされ易く、シリコンはエツチングされにくいので
容易に窓あけすることができる。次いで、第５図に示す
ように膜厚１μ〃Ｉ以１のアルミニウム膜を蒸着し、フ
ォトプロセスによりパターンニングして電極１６とする
。Next, as shown in FIG. 4, using the photoresist top 10 as a mask, the thick foil F'5LOB layer 18 is etched with a hydrofluoric acid solution to form a window. Although the film is a thick 5102 film with a thickness of 1 .mu.m, it can be easily etched by hydrofluoric acid since Sin is easily etched and silicon is difficult to be etched. Next, as shown in FIG. 5, an aluminum film having a thickness of 1 μm or more is deposited and patterned by a photo process to form an electrode 16.
このようにして、フィールＦ Ｓｉｎｇ Ｉｌｌを抵抗
素子領域まで拡げて、フィールドＳ３−０２膜中に電極
を形成すれば、エピタキシャル層を挾んで介在させるこ
となく、埋没拡散層からなる抵抗素子の抵抗値のバラツ
キは減少する。In this way, by extending the field F Sing Ill to the resistive element region and forming an electrode in the field S3-02 film, the resistance value of the resistive element consisting of the buried diffusion layer can be increased without intervening the epitaxial layer. The variation in will be reduced.
１記実施例はフィールド５ｊ−０＋ １ｍがシリコン基
板まで達する工Ｓｏプレーナ構造で説明したが、本発明
は表面にのみフィールドＳｉＯ２膜を形成するＯ８Ｔ構
造にも適用することができる。Although the first embodiment has been described using an SO planar structure in which the field 5j-0+1m reaches the silicon substrate, the present invention can also be applied to an O8T structure in which a field SiO2 film is formed only on the surface.
（ｆ′）発明の効果
以上の説明から判るように、本発明によれば工Ｃ内の低
抵抗素子の抵抗値の変動が少なくなって、工Ｃの特性、
特に出力特性の安定化に寄与するものである。(f') Effects of the invention As can be seen from the above explanation, according to the present invention, the fluctuation in the resistance value of the low resistance element in the circuit C is reduced, and the characteristics of the circuit C are improved.
In particular, it contributes to stabilizing the output characteristics.
第１図は従来の抵抗素子の構造断面図、第２図ないし第
５図は本発明にか＼る抵抗素子の形成工程＋１＠断面図
である。
図中、１はシリコン基板、２は埋没拡散層、３゜１８は
フィールド５１０２膜、４はエピタキシャル層、５は電
極コンタクト層、６．１６は電極、７は５１０２嘆、１
０はフォトレジヌト膜を示す。
第１図
を
第２ｍ
第３図
第４図
第５図FIG. 1 is a cross-sectional view of the structure of a conventional resistance element, and FIGS. 2 to 5 are cross-sectional views of the process of forming the resistance element according to the present invention. In the figure, 1 is a silicon substrate, 2 is a buried diffusion layer, 3°18 is a field 5102 film, 4 is an epitaxial layer, 5 is an electrode contact layer, 6.16 is an electrode, 7 is a 5102 layer, 1
0 indicates a photoresinut film. Figure 1 to 2m Figure 3 Figure 4 Figure 5
Claims (1)
とのエビタキシャ／Ｉ／層と、埋没拡散層上面に及ぶ厚
いフィールド二酸化シリコン膜とを具備し、該フィール
ド二酸化シリコン膜を窓あけして、埋没拡散層に直接接
続する抵抗素子Ｗ、極を形成して成る抵抗素子が含まれ
ることを特徴とする半導体装置。The method includes a buried diffusion layer formed in a semiconductor substrate, an epitaxy/I/layer with the buried diffusion layer, and a thick field silicon dioxide film extending over the top surface of the buried diffusion layer, and the field silicon dioxide film is provided with a window. 1. A semiconductor device comprising: a resistive element W directly connected to a buried diffusion layer; and a resistive element forming a pole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9947082A JPS58216453A (en) | 1982-06-09 | 1982-06-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9947082A JPS58216453A (en) | 1982-06-09 | 1982-06-09 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58216453A true JPS58216453A (en) | 1983-12-16 |
Family
ID=14248195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9947082A Pending JPS58216453A (en) | 1982-06-09 | 1982-06-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58216453A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6476756A (en) * | 1987-09-18 | 1989-03-22 | Nec Corp | Semiconductor integrated circuit device and manufacture thereof |
-
1982
- 1982-06-09 JP JP9947082A patent/JPS58216453A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6476756A (en) * | 1987-09-18 | 1989-03-22 | Nec Corp | Semiconductor integrated circuit device and manufacture thereof |
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