JPS6045016A - Formation of functional element - Google Patents

Formation of functional element

Info

Publication number
JPS6045016A
JPS6045016A JP15272983A JP15272983A JPS6045016A JP S6045016 A JPS6045016 A JP S6045016A JP 15272983 A JP15272983 A JP 15272983A JP 15272983 A JP15272983 A JP 15272983A JP S6045016 A JPS6045016 A JP S6045016A
Authority
JP
Japan
Prior art keywords
silicon
substrate
film
single crystal
antimony
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15272983A
Other languages
Japanese (ja)
Inventor
Hiroshi Hayama
浩 葉山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15272983A priority Critical patent/JPS6045016A/en
Publication of JPS6045016A publication Critical patent/JPS6045016A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

PURPOSE:To control the transfer of a boundary between the high impurity concentration region and the low impurity concentration region of a functional element according to high temperature treatment by a method wherein an Si substrate containing arsenic and antimony as to make at least one side of them to have the specified resistivity is used, and a film having the specified resistivity is used as a single crystal Si film. CONSTITUTION:A single crystal silicon film 5 is grown epitaxially on a silicon single crystal substrate 4, then a functional element is formed in the silicon film 5 thereof, and at least a part of the silicon substrate 4 is removed. A substrate containing as to make impurities of at least one side of arsenic or antimony to have resistivity of 0.015OMEGA.cm or more is used as the silicon substrate 4 at formation of the functional element containing such a peocess, and moreover, a film having resistivity of 0.068OMEGA.cm or more is used as the single crystal silicon film 5. Because the diffusion coefficients of arsenic and antimony are small, when a substrate grown with a silicon epitaxial layer introduced with arbitrary impurities on the low resistance silicon substrate containing only arsenic, only antimony or only arsenic and antimony is used, the silicon single crystal film having arbitrary impurity concentration can be obtained.

Description

【発明の詳細な説明】 本発明は、機能素子の形成方法に関する。[Detailed description of the invention] The present invention relates to a method for forming a functional element.

シリコン単結晶膜に機能素子を製造する方法の1つとし
て単結晶シリコン基板上にシリコンエピタキシャル層を
成長させ、このエピタキシャル層に素子を形成し、次に
裏面からシリコン基板をエツチングし、シリコンエピタ
キシャル層を残す方法がある。
One of the methods for manufacturing functional devices in a silicon single crystal film is to grow a silicon epitaxial layer on a single crystal silicon substrate, form devices on this epitaxial layer, and then etch the silicon substrate from the back side to form a silicon epitaxial layer. There is a way to leave it behind.

素子として社、LSIやセンサなとである。Elements include electronic devices, LSIs, and sensors.

LSIの製造にこの方法を適用する場合、トランジスタ
等の素子を形成したシリコンエピタキシャル層を絶縁物
上に移しかえることになるので寄生容量が減少する等の
メリットがあり、また何層も積みかさねることもできる
。またセンサの製造にこの方法を適用する場合というの
は圧力センサ等でシリコンの薄膜を制御よく形成したい
場合である。
When this method is applied to LSI manufacturing, the silicon epitaxial layer on which elements such as transistors are formed is transferred onto an insulator, which has the advantage of reducing parasitic capacitance, and also eliminates the need to stack multiple layers. You can also do it. Further, this method is applied to the manufacture of sensors when it is desired to form a silicon thin film in a pressure sensor or the like with good control.

以上述べたような機能素子の形成方法にも2f!!類あ
る。1つの方法は、第1図の様に、シリコン基板10表
面に高濃度にtなう素を導入したシリコン層2を形成し
、その上にシリコンエピタキシャル層3を成長させた基
板を用いる方法である。通常のシリコンのエツチングに
用いられている弗酸と硝酸の混合液に対して、高濃度に
ほう素を導入したシリコン層2は、エツチングレートが
非常に低いため、裏面からシリコン基板のエツチングを
行なった場合に、高濃度にはう素を導入したシリコン層
2でエツチングを停止させることが可能である。このこ
とを利用して、基板を裏面からエツチングし、高濃度に
#1う素を導入したシリコン層2とその上に素子を形成
したシリコンエピタキシャル層3で構成された機能素子
を形成することができる。
2f! also applies to the method of forming functional elements as described above! ! There are many kinds. One method, as shown in FIG. 1, is to use a substrate in which a silicon layer 2 into which t is introduced at a high concentration is formed on the surface of a silicon substrate 10, and a silicon epitaxial layer 3 is grown thereon. be. Compared to a mixture of hydrofluoric acid and nitric acid that is normally used for silicon etching, the etching rate of the silicon layer 2 containing boron at a high concentration is very low, so the silicon substrate is etched from the back side. In this case, it is possible to stop the etching with the silicon layer 2 into which boron is introduced at a high concentration. Taking advantage of this fact, it is possible to form a functional device consisting of a silicon layer 2 into which #1 borium is introduced at a high concentration and a silicon epitaxial layer 3 on which the device is formed by etching the substrate from the back side. can.

しかし、高濃度にはう素を導入したシリコン層上には良
質のシリコンエピタキシャル層が成長させKくいという
欠点がある。また、はう素の拡散係数が大きいためにシ
リコンエピタキシャル層3の堆積時に、高濃度にほう素
を導入したシリコン1台2からのほう素の拡散が著しく
、高抵抗P型シリコンエピタキシャル層や薄いn型シリ
コンエピタキシャル層が成長させにくい等の欠点がある
However, there is a drawback that it is difficult to grow a high-quality silicon epitaxial layer on a silicon layer into which boron is introduced at a high concentration. In addition, since the diffusion coefficient of boron is large, when depositing the silicon epitaxial layer 3, the diffusion of boron from the silicon 1 2 into which boron is introduced at a high concentration is significant, resulting in a high resistance P-type silicon epitaxial layer or a thin silicon epitaxial layer. There are drawbacks such as difficulty in growing an n-type silicon epitaxial layer.

一方、裏面からシリコン基板をエツチングし、シリコン
エピタキシャル層のみを残すもう1つの方法は、第2図
に示すようなシリコン基板とじて抵抗率が0.015Ω
・α以下の低抵抗基板4を用い、その上に抵抗率006
8Ω・−以上のシリコンエピタキシャル層5を成長させ
た基板を用いるものである。ザ・エレクトロケミカル・
ソザエティ、エクステンプイツト・アブストラクツ(’
l’he Electro−chemical 5oc
iety Extended Abstracts)第
’12−1巻、74ページに詳細に述べられているよう
に、低抵抗シリコン基板のエツチングレートが高抵抗シ
リコンエピタキシャル層のエツチングレートに比較し、
て大きい性質を有する、弗酸と硝酸と酢酸が1対3対8
の構成比のシリコンエッチャントがある。これを抵抗率
0.015Ω・m以−トの基板4を裏面からエツチング
し、選択的に抵抗率p、068Ω・α以上のシリコンエ
ピタキシャル層5を露出させることができる。この小を
利用してシリコンエピタキシャル層5に機能素子を形成
することができる。
On the other hand, another method is to etch the silicon substrate from the back side, leaving only the silicon epitaxial layer.
・Use a low resistance substrate 4 with a resistivity of 006 or less on it.
A substrate on which a silicon epitaxial layer 5 of 8Ω·- or more is grown is used. The Electrochemical
Society, Expedited Abstracts ('
l'he Electro-chemical 5oc
As detailed in ``Iity Extended Abstracts'' Vol. 12-1, page 74, the etching rate of a low-resistance silicon substrate is higher than that of a high-resistance silicon epitaxial layer.
Hydrofluoric acid, nitric acid, and acetic acid have a 1:3:8 ratio.
There is a silicon etchant with a composition ratio of . By etching the substrate 4 having a resistivity of 0.015 Ω·m or more from the back side, it is possible to selectively expose the silicon epitaxial layer 5 having a resistivity p of 068 Ω·α or more. Functional elements can be formed in the silicon epitaxial layer 5 by utilizing this small size.

しかしながら、この第2の方法を用いても通常の低抵抗
基板を用いると高不純物濃度領域(基板)4と低不純物
濃度領域(エピタキシャル層)5との境界が高温処理に
より容易に移動する。寸だ、高不純物濃度領域4と低不
純物濃度領域5との遷移領域が高温処理により容易に拡
大してしオう。
However, even if this second method is used, if a normal low resistance substrate is used, the boundary between the high impurity concentration region (substrate) 4 and the low impurity concentration region (epitaxial layer) 5 will easily move due to high temperature treatment. Indeed, the transition region between the high impurity concentration region 4 and the low impurity concentration region 5 is easily expanded by high temperature treatment.

そのだめ、シリコンエピタキシャル層5の濃度全均一な
低濃度に保つことは困難であシ、そこに形成したあるい
はその後に形成する機能素子の特性が劣化してしまう。
Therefore, it is difficult to keep the concentration of the silicon epitaxial layer 5 uniformly low throughout, and the characteristics of functional elements formed thereon or subsequently formed will deteriorate.

本発明はこのような欠点を除去した機能素子の形成方法
を提供することを目的とする。
An object of the present invention is to provide a method for forming a functional element that eliminates such drawbacks.

本発明によれば、シリコン単結晶基板上に単結晶シリコ
ン膜をエピタキシャル成長し、次いでこのシリコン膜に
機能素子を形成し、次いで前記シリコン基板の少なくと
も一部分を除去する工程を含む機能素子の形成方法にお
いて、前記シリコン基板として砒素あるいはアンチモン
のうちから選んだ少なくとも一方の不純物が抵抗率00
15Ω・α以下になるように含まれた基板を用い、しか
も前記単結晶シリコン膜として、抵抗率0.068Ω・
α以上の膜を用いることを特徴とする機能素子の形成方
法が得られる。
According to the present invention, a method for forming a functional element includes the steps of epitaxially growing a single crystal silicon film on a silicon single crystal substrate, then forming a functional element on the silicon film, and then removing at least a portion of the silicon substrate. , the silicon substrate contains at least one impurity selected from arsenic and antimony, and has a resistivity of 00.
A substrate with a resistivity of 15Ω・α or less is used, and the single crystal silicon film has a resistivity of 0.068Ω・
A method for forming a functional element characterized by using a film having a thickness of α or more can be obtained.

前記した第2の方法において(1,J用される低抵抗基
板の不純物と[7てはほう素、アルミニウム、リン、砒
素、アンチモンが原理的には可能である。
In the second method described above, it is possible in principle to use impurities of the low resistance substrate used (1, J) and [7] such as boron, aluminum, phosphorus, arsenic, and antimony.

しかし、はう素、アルミニウム、リンは大きな拡散係数
を有している。砒素、アンチモンは拡散係数が小さい。
However, boronate, aluminum, and phosphorus have large diffusion coefficients. Arsenic and antimony have small diffusion coefficients.

そのため、砒素のみ、または、アンチモンのみ、または
砒素とアンチモンのみしか含まない低抵抗シリコン基板
上に、任意の不純物な導入したシリコンエピタキシャル
層を成長させた基板を用いれば、前記した第2の方法に
より、任意の不純物濃度を有するシリコン単結晶膜を得
ることが可能となる。
Therefore, if a silicon epitaxial layer containing any impurity is grown on a low-resistance silicon substrate containing only arsenic, only antimony, or only arsenic and antimony, the second method described above can be used. , it becomes possible to obtain a silicon single crystal film having an arbitrary impurity concentration.

本発明によれば、高温処理による高不純物濃度領域と低
不純物濃度領域との境界の移動を抑制できる。また、高
温処理による高不純物濃度領域と低不純物濃度領域との
間に存在する遷移領域の拡大も抑制できる。そのため、
任意の不純物と不純物濃度を有する薄いシリコンエピタ
キシャル層で構成されるシリコン単結晶膜を製造できる
According to the present invention, movement of the boundary between the high impurity concentration region and the low impurity concentration region due to high temperature treatment can be suppressed. Furthermore, expansion of the transition region between the high impurity concentration region and the low impurity concentration region due to high temperature treatment can also be suppressed. Therefore,
A silicon single crystal film consisting of a thin silicon epitaxial layer with arbitrary impurities and impurity concentrations can be manufactured.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は第1の従来方法によるシリコン1r結晶膜製造
時に用いられる基板の構造を示す概略断面図であり、1
−1、シリコン基板、2は、高濃度にほう素を樽入した
シリコン層、3は、シリコンエピタキシャル層である。 第2図は、第2の従来方法によるシリコン単結晶膜製造
時に用いられる基板の構造を月−す概略断面図であり、
4は抵抗率0015Ω・口取下の低抵抗シリコン基板、
5は抵抗率0.068o・副以上のシリコンエピタキシ
ャル層である。 代理人ブl511士 内 原 Y7 第1図 63− 72図
FIG. 1 is a schematic cross-sectional view showing the structure of a substrate used in manufacturing a silicon 1r crystal film by a first conventional method.
-1 is a silicon substrate, 2 is a silicon layer containing boron at a high concentration, and 3 is a silicon epitaxial layer. FIG. 2 is a schematic cross-sectional view showing the structure of a substrate used in manufacturing a silicon single crystal film by a second conventional method;
4 is a low-resistance silicon substrate with a resistivity of 0015Ω and a bottom edge.
5 is a silicon epitaxial layer having a resistivity of 0.068° or more. Agent BL511 Uchihara Y7 Figure 1 Figures 63-72

Claims (1)

【特許請求の範囲】[Claims] シリコン単結晶基板上に単結晶シリコン膜をエピタキシ
ャル層長し、次いでこのシリコン膜に機能素子を形成し
、次いで前記シリコン基板の少なくとも一部分を除去す
る工程を含む機能素子の形成方法において、前記シリコ
ン基板と七で砒素あるいはアンチモンのうちから選んだ
少なくとも一方の不純物が抵抗率Ofl 15Q−cm
以下になるように含まれた基板を用い、しかも前記単結
晶シリコン膜として、抵抗率0D68Ω・百以上の膜を
用いることを特徴とする機能素子の形成方法。
A method for forming a functional element comprising the steps of epitaxially growing a single crystal silicon film on a silicon single crystal substrate, then forming a functional element on this silicon film, and then removing at least a portion of the silicon substrate. and at least one impurity selected from arsenic or antimony has a resistivity Ofl 15Q-cm
A method for forming a functional element, characterized in that a substrate having the following properties is used, and a film having a resistivity of 0D68Ω and 100 or more is used as the single crystal silicon film.
JP15272983A 1983-08-22 1983-08-22 Formation of functional element Pending JPS6045016A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15272983A JPS6045016A (en) 1983-08-22 1983-08-22 Formation of functional element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15272983A JPS6045016A (en) 1983-08-22 1983-08-22 Formation of functional element

Publications (1)

Publication Number Publication Date
JPS6045016A true JPS6045016A (en) 1985-03-11

Family

ID=15546876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15272983A Pending JPS6045016A (en) 1983-08-22 1983-08-22 Formation of functional element

Country Status (1)

Country Link
JP (1) JPS6045016A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63170914A (en) * 1987-01-09 1988-07-14 Fuji Electric Co Ltd Manufacture of semiconductor device
US7341787B2 (en) 2004-01-29 2008-03-11 Siltronic Ag Process for producing highly doped semiconductor wafers, and dislocation-free highly doped semiconductor wafers

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63170914A (en) * 1987-01-09 1988-07-14 Fuji Electric Co Ltd Manufacture of semiconductor device
US7341787B2 (en) 2004-01-29 2008-03-11 Siltronic Ag Process for producing highly doped semiconductor wafers, and dislocation-free highly doped semiconductor wafers

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