JPS5844761A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5844761A JPS5844761A JP57104839A JP10483982A JPS5844761A JP S5844761 A JPS5844761 A JP S5844761A JP 57104839 A JP57104839 A JP 57104839A JP 10483982 A JP10483982 A JP 10483982A JP S5844761 A JPS5844761 A JP S5844761A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline
- layer
- high resistance
- film
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 15
- 239000012535 impurity Substances 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 150000002500 ions Chemical class 0.000 abstract 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体装置の製造方法に関するもので、特に
多結晶シリコンを高抵抗として用いる技術に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a technique using polycrystalline silicon as a high resistance material.
半導体集積回路装置において、小さな面積内に非常に高
い抵抗を実現する必要にせまられる場合がしばしばある
。例えげMO8型集積回路における負荷抵抗はその一例
である。不純物を含まない、ないしは微量しか含まない
多結晶7リコンは、その目的に合う材料の一つである事
は従来から知られている。また実際に半導体装置に組み
込む方法として、従来知られている方法は、母体となる
プロセスに、さらに高抵抗多結晶クリコンを成長する工
程及びそれを所定の形状に成形するフォトレジスト工程
を追加する方法である。第1図は母体プロセスとして通
常のアルミゲートプロセスを例にとり多結晶シリコンに
よる高抵抗を付加するための従来技術を示したものであ
る。In semiconductor integrated circuit devices, it is often necessary to realize very high resistance within a small area. For example, a load resistor in an MO8 type integrated circuit is one example. It has been known for a long time that polycrystalline 7-licon, which does not contain any impurities or contains only trace amounts of impurities, is one of the materials suitable for this purpose. In addition, a conventionally known method for actually incorporating it into a semiconductor device is to add a step of growing high-resistance polycrystalline silicon and a photoresist step of molding it into a predetermined shape to the base process. It is. FIG. 1 shows a conventional technique for adding high resistance using polycrystalline silicon, taking as an example a normal aluminum gate process as a base process.
まず第1図(イ)K示す様に通常の製法に従い、半導体
基板+11の表面を酸化膜(2)で被い、ソース、ドレ
インを形成するための拡散窓+31 +41を開孔する
。First, as shown in FIG. 1(a)K, the surface of a semiconductor substrate +11 is covered with an oxide film (2) according to a normal manufacturing method, and diffusion windows +31 to +41 for forming sources and drains are opened.
次に第1図(ロ)K″示す様に拡散によりソース(5)
、ドレイン(61を形成すると共にその表面を酸化膜(
7)で被う。次に第1図(ハ)に示す様にゲート領域の
酸化膜を除去し、新たにゲート酸化膜(8)を成長させ
る。Next, as shown in Figure 1 (b) K'', the source (5) is formed by diffusion.
, a drain (61) is formed and its surface is covered with an oxide film (
Cover with 7). Next, as shown in FIG. 1(c), the oxide film in the gate region is removed and a new gate oxide film (8) is grown.
ここまでは通常のアルミゲートの製法であり、多結晶シ
リコンの高抵抗を導入するためには、さらに第1図に)
に示す様に多結晶シリコン層を全面に成長し、所定の形
状に成形して抵抗体(91を形成する。次に第1図(ホ
)K示す様に熱酸化により抵抗体(9)の表面を酸化膜
αeで保護する。次に第1図(ハ)K示す様に抵抗の両
端のコンタクト孔111103及びソース、ドレインの
コンタクト孔(13(14)を開孔する。次に第1図(
ト)K示す様に所定のアルミ配線α9を設けて装置は完
成する。この様に1従来の方法は母体プロセスに多結晶
7リコンの成長工程及び所定の形状に成形するための写
真蝕刻(P、R)工程を追加する事によって達成されて
い友ため、工程かは′ ん雑となり、それだけ作
られた半導体装置の歩留り、信頼性は低いものであった
。Up to this point, the manufacturing method for an ordinary aluminum gate has been described.
A polycrystalline silicon layer is grown on the entire surface as shown in FIG. The surface is protected with an oxide film αe. Next, contact holes 111103 at both ends of the resistor and contact holes (13 (14)) for the source and drain are opened as shown in FIG. (
g) As shown in K, a predetermined aluminum wiring α9 is provided to complete the device. In this way, the conventional method was achieved by adding a polycrystalline 7-licon growth step and a photo-etching (P, R) step for forming into a predetermined shape to the base process, so the process As a result, the yield and reliability of the semiconductor devices produced were low.
本発明の目的はかかる欠点を解決した。工程を増大する
ことなく得られ、信頼性の優れた多結晶7リコン層を有
する半導体装置の製造方法を提供することにある。The object of the present invention is to overcome such drawbacks. It is an object of the present invention to provide a method for manufacturing a semiconductor device having a polycrystalline silicon layer with excellent reliability, which can be obtained without increasing the number of steps.
本発明はシリコンゲートプロセスに、もとモト用いられ
ている多結晶シリコン層に着目し、その一部を不純物の
添加による導体化から保護する事によって高抵抗のまま
残すことKより、導体層としての低抵抗領域と共に一部
を抵抗1体としての高抵抗領域に形成することを基本と
するものである。The present invention focuses on the polycrystalline silicon layer originally used in the silicon gate process, and protects a part of it from becoming conductive due to the addition of impurities, leaving it with high resistance. The basic idea is to form a high-resistance region as a single resistor along with a low-resistance region.
本発明による半導体装置の製造方法は半導体基板と、該
基板を被う絶縁被膜と、該絶縁被膜上に設けられた多結
晶シリコン導体層とを有する半導体装置の製造方法にお
いて、低濃度の不純物を含む多結晶シリコン被膜を上記
基板上に形成する工程と、上記多結晶シリコン被膜の所
定の部分を7オトレジストで被う工程と、しかる後不純
物を上記フォトレジストマスクとして上記多結晶7リコ
ン被膜に注入する工程と、上記フォトレジストを除去す
る工程とを含み。A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a semiconductor substrate, an insulating film covering the substrate, and a polycrystalline silicon conductor layer provided on the insulating film. forming a polycrystalline silicon film on the substrate, covering a predetermined portion of the polycrystalline silicon film with a 7-resist, and then injecting impurities into the poly-7 resist as the photoresist mask. and removing the photoresist.
上記所定の部分を抵抗体とし、それ以外の上記多結晶シ
リコン被膜と上記導体層とすることを特徴とする〇かか
る本発明では、上記不純物の多結話シリコンへの不純物
の添加のためのマスクとして用いるために多結晶シリコ
ン上への選択的形成および添加後の除去を容易に行なう
ことができる。またマスクが7オトレジスト自体である
ためにバタン精度も良い。The present invention is characterized in that the predetermined portion is used as a resistor, and the other portions are used as the polycrystalline silicon film and the conductor layer. In the present invention, a mask for adding the impurity to the polycrystalline silicon is provided. It can be selectively formed on polycrystalline silicon and easily removed after addition for use as a silicon oxide. Also, since the mask is made of 7-otoresist itself, the batting accuracy is good.
さらに本発明ではフォトレジストを除去して多結晶シリ
コン上に絶縁膜を直接被覆するためKこめ絶縁膜の表面
を平坦とすることができ、よってこの上に設けられる配
線が断切れすることなく高密度に設けることができる。Furthermore, in the present invention, since the photoresist is removed and the insulating film is directly coated on the polycrystalline silicon, the surface of the insulating film can be made flat, so that the wiring provided thereon can be raised without being cut off. It can be provided in different densities.
次に本発明の一実施例をその構成方法と共に第2図を用
いて説明する。まず第2図(イ)K示す様に。Next, an embodiment of the present invention will be described with reference to FIG. 2 along with its construction method. First, as shown in Figure 2 (a) K.
通常のクリコンゲートMO8の製法に従いシリコン基板
Qυの表rfiをフィールド酸化at(2)で被い、ト
ランジスタを形成する領域にゲート酸化a11IJt−
形成する。次に第2図(CI)K示す様に多結晶シリコ
ン配線と拡散層とを直接接続する丸めのコンタクト孔@
を開孔する。次に第2図(ハ)に示す様に%多結晶シリ
コンを成長、成形し、ゲート電極(ハ)及び配線となる
部分(ハ)を形成し、電極(ハ)をマスクとしてゲート
酸化膜をエツチングし、ソース、ドレインを形成する部
分Q1.@を開孔する。次に第2図に)に示す様に多結
晶シリコン配線(ハ)のうち抵抗とする部分(至)を7
オトレジスト(イ)で被い基板全面にイオン注入をほど
こす事によ抄ソース(至)、ドレイン(31)を形成す
ると同時にゲート電極(25)、配線(26)を導体化
する。次に第2図(ホ)K示す様に、フォトレジストを
除去して全面をシリコン酸化膜(32)で被う。次に第
2図ト)に示す様に必要なコンタクト孔(33)を開孔
し、第2図(ト)K示す様に、所定のアルミ配線(34
)を設けて装置は完成する。The surface rfi of the silicon substrate Qυ is covered with field oxidation at(2) according to the usual manufacturing method of the crystal gate MO8, and the gate oxidation a11IJt- is applied to the region where the transistor is to be formed.
Form. Next, as shown in Fig. 2 (CI) K, a round contact hole @ which directly connects the polycrystalline silicon wiring and the diffusion layer
Drill a hole. Next, as shown in Figure 2 (c), % polycrystalline silicon is grown and molded to form a gate electrode (c) and a portion that will become a wiring (c), and a gate oxide film is formed using the electrode (c) as a mask. Portion Q1 to be etched to form source and drain. Drill @. Next, as shown in Figure 2), the part (to) of the polycrystalline silicon wiring (c) that will be the resistor is 7
By performing ion implantation over the entire surface of the substrate covered with photoresist (a), a source (to) and a drain (31) are formed, and at the same time, the gate electrode (25) and wiring (26) are made conductive. Next, as shown in FIG. 2(e)K, the photoresist is removed and the entire surface is covered with a silicon oxide film (32). Next, as shown in Figure 2 (G), the necessary contact holes (33) are drilled, and as shown in Figure 2 (G), the predetermined aluminum wiring (34) is opened.
) to complete the device.
以上の如く1本発明によればシリコンゲート構造を構成
するためKもともと用いられる多結晶7IJ 9ン層を
有効に利用して高抵抗としての多結晶クリコンを成長す
る工程を追加する事なくシリコン基板と同時に高抵抗領
域を形成することができる。またこのためのマスクとし
てフォトレジストを用いるためにその被着および除去が
容易に行なえる。また本発明は多結晶シリコンの配線の
一部として高抵抗を作成するため配線と接続するための
コンタクトを必要としない。即ち第3図(イ)に部分平
面図を示す様に従来法では特別に設けた高抵抗シリコン
(9)とアルミニウム配線(ハ)を接続するためにはコ
ンタクト孔01)03を要する。しかし本発明によれば
第3図(ロ)に示す様に導体としての多結晶シリコン(
ハ)の一部分を高抵抗体(至)として残しているため何
らコンタクトを要さず、コンタクトの数を増す必要がな
く歩留的にも優れている。As described above, according to the present invention, by effectively utilizing the polycrystalline layer originally used to form a silicon gate structure, a silicon substrate can be grown without adding a step of growing polycrystalline silicon as a high-resistance layer. At the same time, a high resistance region can be formed. Furthermore, since a photoresist is used as a mask for this purpose, it can be easily applied and removed. Furthermore, since the present invention creates a high resistance as part of the polycrystalline silicon wiring, there is no need for a contact for connection to the wiring. That is, as shown in a partial plan view in FIG. 3(a), in the conventional method, contact holes 01 and 03 are required to connect the specially provided high-resistance silicon (9) and aluminum wiring (c). However, according to the present invention, polycrystalline silicon (
Since a part of c) is left as a high resistance element, no contacts are required, and there is no need to increase the number of contacts, resulting in an excellent yield.
またマスクとしての7オトレジストは除去されているた
め、多結晶クリコン上の絶縁膜は平坦であり、多層配線
構造に適したものとなっている。Furthermore, since the 7th photoresist serving as a mask has been removed, the insulating film on the polycrystalline silicon is flat and suitable for a multilayer wiring structure.
なお本発明は上述した実施例に限定されるものではなく
1例えば第2図(ト)K示したアルず配線(34)を多
結晶シリコンにより多結晶シリコン配線6と同時に形成
しても良く、また多結晶シリコンへの不純物拡散等を濃
度を変更して選択的に行なうことにより複数の7−ト抵
抗を有する抵抗領域を形成してもよいのである。Note that the present invention is not limited to the above-mentioned embodiments; for example, the aluminum wiring (34) shown in FIG. Further, by selectively performing impurity diffusion into polycrystalline silicon by changing the concentration, a resistance region having a plurality of 7-t resistances may be formed.
第1図は従来技術による多結晶シリコンの高抵抗部を有
する半導体装置の形成方法を順次示す断面図であり、第
2図は本発明の実施例による半導体装置の形成方法を説
明する断面図であシ、第3図は従来技術と本発明による
技術のコンタクトの取り方を説明する平面図であり、@
3図(1)は従来技術による。第3図(blは本発明に
よるものである。
図中の符号
1.21・・・・・・半導体基板、2,7,8,10,
22゜23.32・・・・・・酸化膜、3,4.27.
“28・・・・・・窓、11.12,13.14.24
・・・・・・コンタクト孔、5.“10・・・・・・ソ
ース、6,31・・・・・・ ドレイン、25・・・・
・・ゲート基板、20・・・・・・ホトレジスト、9.
29・・・・・・抵抗体、15.34・・・・・・アル
ミ配線。
#1回(ロノ
第 / レフ (パラ
ク
第1 則(二ノ
秦l聞(尤ノ
第 /16(ヘノ
4η /7(トノ
3z
冶Z目(ホ2
第Z 目(へ2
めZ目()ン
育53圀 (イノ
第8図(ロノFIG. 1 is a cross-sectional view sequentially illustrating a method for forming a semiconductor device having a high-resistance portion of polycrystalline silicon according to the prior art, and FIG. 2 is a cross-sectional view illustrating a method for forming a semiconductor device according to an embodiment of the present invention. Figure 3 is a plan view explaining how to make contact between the conventional technology and the technology according to the present invention.
Figure 3 (1) is based on the prior art. FIG. 3 (bl is according to the present invention. Reference numbers 1.21 in the figure...semiconductor substrate, 2, 7, 8, 10,
22°23.32...Oxide film, 3,4.27.
“28...window, 11.12, 13.14.24
...Contact hole, 5. “10... Source, 6, 31... Drain, 25...
...Gate substrate, 20...Photoresist, 9.
29...Resistor, 15.34...Aluminum wiring. #1 (Rono no. Iku 53 area (Ino 8th figure (Rono)
Claims (1)
に設けられた多結晶シリコン導体層とを有する半導体装
置の製造方法において、低lII[の不純物を含む多結
晶シリコン被膜を上記基板上に形成する工程と、上記多
結晶7リコン被膜の所定の部分を7オトレジストで被う
工程と、しかる後不純物を上記フォトレジストをマスク
として上記多結晶シリコン被膜に注入する工程と、上記
フォトレジストを除去する工程とを含み、上記所定の部
分を抵抗体とし、それ以外の上記多結晶7リコン被膜と
上記導体層とすることt−特徴とする半導体装置の製造
方法。In a method for manufacturing a semiconductor device having a semiconductor substrate, an insulating cylindrical film covering the substrate, and a polycrystalline silicon conductor layer provided on the insulating film, the polycrystalline silicon film containing impurities of low lII[ a step of covering a predetermined portion of the polycrystalline 7 silicon film with a 7 photoresist; a step of implanting impurities into the polycrystalline silicon film using the photoresist as a mask; A method for manufacturing a semiconductor device, comprising the step of removing a resist, the predetermined portion being used as a resistor, and the remaining portions being the polycrystalline silicon coating and the conductor layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57104839A JPS5844761A (en) | 1982-06-18 | 1982-06-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57104839A JPS5844761A (en) | 1982-06-18 | 1982-06-18 | Manufacture of semiconductor device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9907476A Division JPS5324290A (en) | 1976-08-18 | 1976-08-18 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5844761A true JPS5844761A (en) | 1983-03-15 |
Family
ID=14391513
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57104839A Pending JPS5844761A (en) | 1982-06-18 | 1982-06-18 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5844761A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02504656A (en) * | 1988-06-09 | 1990-12-27 | ウールテック リミテッド | Solvent treatment of animal hair |
-
1982
- 1982-06-18 JP JP57104839A patent/JPS5844761A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02504656A (en) * | 1988-06-09 | 1990-12-27 | ウールテック リミテッド | Solvent treatment of animal hair |
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