JPS61168260A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To readily manufacture bipolar transistors of high density in a high yield at a high speed by forming a base leading electrode and an emitter electrode at an ultrafine separating interval by a self-alignment. CONSTITUTION:After an oxide preventive film 26, an accumulated film 27 and an accumulated film 28 including an impurity are formed on an active region 23 of a transistor, a semiconductor film 30 is formed. Then, an impurity is diffused in the semiconductor film 30 from laminated films 26-28 by a heat treatment. Then, a semiconductor film of an impurity diffused region having a fast etching rate is selectively removed by the difference of the etching rate of the film 30, and a region 30b in which the impurity is not diffused is allowed to remain. Subsequently, the films 26-28 are implanted, and other conductive type impurity is implanted to the film 30b. Then, the films 27, 28 are removed, with the film 26 as a mask an insulating film 31 is formed on the film 30b. Then, the film 26 is removed, and windows for diffusing an emitter and contacting the emitter are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a method of manufacturing a high-speed, high-density bipolar type semiconductor element.

It is something to do.

In order to achieve high speed and high density in conventional bipolar transistors, it is necessary to miniaturize the pattern and reduce the junction capacitance. Therefore, conventional studies have been conducted to miniaturize the pattern and reduce the junction capacitance by forming the base lead electrode with a polycrystalline silicon film (PolySi film). Example Eva, IEEE
JOURNAL 0FSOLID-8TATE CI
RCUITS Vol, 5c-16°No, 5.0CT
OBER1981T:Id, the Po1ySi film 6a which becomes the base extraction electrode is formed by the manufacturing method shown in FIG.

Problems to be Solved by the Invention However, the manufacturing method shown in FIG. 3 has the following problems.

(1) PolyS i film 6 serving as an emitter electrode
It is difficult to form b precisely and finely. The PolySi film 6, which becomes the emitter electrode, is
FIG.
It is formed by etching the Si film 6. However, when forming the boron-doped Po1ySi film 6a, Si02
Boron-doped Po1y S is applied to a part of the periphery under the film 8 region.
It becomes an i-film 6a. Therefore, non-doped) PolySi
It is necessary to side-etch the Si3N4 film 7 so that the film 6 can be etched. Also, non-doped) Poly
Si film 6 and boron doped) PolySi film 6a is completely 6
To separate a, use non-doped) PolySi film 6
It is necessary to etch the film by the thickness of a. Therefore,
A side etch corresponding to at least the thickness of the non-doped Po1ySi film 6 is included.

Therefore, the boron-doped) Po1ySi film 6a intrudes under the S102 film 8 region, and the Si3N4 film 7
Due to the influence of side etching amount, variation in film thickness of non-doped Po1ySi film 6, variation in etching time of Po1y5ii6 (non-doped)
The amount of side etching of the PolySi film 6 is different. Therefore, the pattern dimensions of the non-doped PolySi film 6 which becomes the emitter electrode change, making it difficult to form it precisely and finely.

(2) Stress is likely to occur when forming the 5i02 film 10. Threaded, as shown in Figure 3 0, non-doped) Poly
After separating the Sf film 6 and the boron-doped Po1ySi film 6a by etching, as shown in FIG.
When 2 films are 1o and 1o in total, non-doped Po1y St
Since the space between the film 6 and the boron-doped PolySi film 6a is in the shape of a recess, stress due to oxidation is applied to the recess. In this case, the narrower the interval, the greater the stress. Therefore, if the spacing is narrow, defects are likely to occur due to stress, which causes a decrease in yield.

In view of these conventional problems, it is an object of the present invention to provide a method for manufacturing a semiconductor device having high-speed, high-density bipolar transistors that solves these problems.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a predetermined laminated film consisting of an oxidation prevention film, a deposited film, and a deposited film containing impurities (for example, a PSG film) on the active region of a transistor. After forming a semiconductor film (for example, a Po1y-8i film), an impurity is selectively diffused from the laminated film into the semiconductor film by heat treatment to form an impurity diffusion region. Thereafter, depending on the difference in the etching rate of the semiconductor films, the semiconductor film in the impurity diffusion region where the etching rate is high is selectively removed, and the semiconductor film in the region where the impurity with the slow etching rate is not diffused is left. Thereafter, impurities of the other conductivity type are ion-implanted into the semiconductor film using the laminated film as an implantation mask. Thereafter, after removing the deposited film, an insulating film is formed on the semiconductor film using the anti-oxidation film as a mask. Thereafter, the anti-oxidation film is removed and windows for emitter diffusion and emitter contact are opened.

Effects The present invention has the above-described configuration. (1) The semiconductor film serving as the base lead-out electrode, the emitter diffusion window and the emitter contact window can be formed by self-adhesion on the laminated film pattern.

(2) The separation interval between the semiconductor film on which the pace extraction electrode reaches and the electrode connected to the emitter contact window is:
Since it is determined by the thickness of the insulating film, fine separation between the emitter and the pace electrode is possible.

(3) After removing the semiconductor film in the impurity diffusion region above the active region, an insulating film is formed on the remaining semiconductor film using the anti-oxidation film as a mask, so stress is generated on the semiconductor layer, which is the active region. Therefore, high-yield semiconductor devices without crystal defects can be manufactured.

Embodiment FIG. 1 is for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention, and this semiconductor device has an NPN type bipolar transistor. In FIG. 1, an N+ type buried layer 21 is formed on a P type semiconductor (silicon here) substrate (hereinafter referred to as Si substrate) 20 using a well-known technique.
, P+ type channel stopper layer 22, N type semiconductor layer (
(hereinafter referred to as shrimp layer) 23, separation insulating film (hereinafter referred to as separation S 1
02 film) 24 and an N+ type collector all layer 25 (FIG. 1A).

Next, a silicon nitride film (hereinafter referred to as 513N4 film) 26 as an oxidation prevention film and a silicon oxide film (hereinafter referred to as CV D S 102 film) as a deposited film are deposited on the 81 substrate 20.
27. A phosphorus-doped silicon oxide film (hereinafter referred to as a PSG film) 28 is sequentially formed as a deposited film containing impurities by the CVD method (FIG. 1B).

Next, a photo-etching technique is used on a predetermined region of the shrimp layer 23 that will become the active region of the transistor, and the PS
G film 28, CV D -S i○2 film 27 and Si3
A laminated film pattern 29 made of N4 film 26 is selectively formed. After that, a polycrystalline silicon film (hereinafter referred to as Po1y-81 film) 30 is formed as a semiconductor film on the Si substrate 2o by CVD.
It is formed by method D (FIG. 1C).

Next, the Si substrate 2o is subjected to heat treatment. For example, Si
The substrate 20 is heated at 100° C. for 30 minutes.

At this time, phosphorus is diffused from the PSG film 28 into the Poly-3i layer 30 on the laminated film pattern 29, forming an N type diffusion region 30a (FIG. 1D).

Next, the N type Poly-8i film 30a is removed by etching. As the etching solution, for example, a mixed solution consisting of nitric acid, hydrofluoric acid and acetic acid is used. In this case, the N-type P01y-8i film 30a has an etching rate about 10 to 20 times faster than the P01y-3t film 30 in which phosphorus is not diffused. Therefore, the Po1y−
The N+ type Po1y-8i film 30a can be removed without substantially etching the 8i layer 3o, and the Po1y-3i film 30a is formed in a region other than on the laminated film pattern 29.
0 can remain.

Thereafter, only the PSG film 28 is removed by etching, and using the remaining CVD-S i○2 film as an implantation mask, a P-type impurity is implanted into the Po1y-3t film 30.
ions are implanted to selectively form a P+ type Po1y-8i film 30b (FIG. 1E).

Next, the CVD Si02 film 27 is removed by etching, and the N-type epitaxial layer 23 is etched using a photoetching technique.
Door-shaped Po1y-3t film 3ob only on a predetermined area containing
form a selection. Thereafter, using the Si3N4 film 26 as an oxidation mask, the P+ type Po1y-8 is heated by thermal oxidation.
A silicon oxide film (hereinafter referred to as S102 film) 3 is formed on the T film 30b.
form 1. At this time, the P+ type Po1y-8i film 3
Boron diffuses from 0b, and a P+ type diffusion layer 32 serving as a graft base is formed directly under the P+ type Po1y-8i film (FIG. 1F).

Next, the Si3N4 film 26 is removed by etching, an emitter diffusion window is opened, and using the SiO2 film 31 as an implantation mask, boron and arsenic ions are implanted into the N-type shrimp layer 23 in the active region, and heat treatment is performed. P as the active base
A swelling diffusion layer 33 and an N+ type diffusion layer 34 serving as an emitter are sequentially formed (FIG. 1G).

Next, using well-known techniques, a pace withdrawal electrode is used.
lx LeP" type Po1y-8i film 3ob S z 0
After opening a contact window in the second film 31, aluminum wiring (
35 (hereinafter referred to as AI2 wiring) is formed. In this way,
As shown in FIG. 1H, an NPN type bipolar transistor can be formed.

Next, FIG. 2 shows an embodiment of an NPN type bipolar transistor whose emitter is made of a Po1y-8t film.

Before forming the base and emitter of the active region of the transistor, the same steps are performed using the method shown in FIGS. 1A to 1F.

Next, the Si3N4 film 26 is removed by etching, an emitter diffusion window is opened, and boron ions are implanted into the N-type epitaxial layer 23 in the active region, and heat treatment is performed to form a P-swelled diffusion layer 4Q that will become an active base. do. After that, this P swelling diffusion layer 4
An N+ type Po1y-8i film 41 is selectively formed on the N+ type collector all layer 25 and is subjected to heat treatment to form a Po1y-8i film 41.
N+ type Po1y-3i film 41 that becomes a 1y-8i emitter
a and Po1y-3i N+ type Po which becomes the contact
1y-8t M4 lb respectively (Fig. 2A).

Next, using a well-known technique, a contact window is opened in the Si2 film 31 on the P+ type Po1y-3i film 30b, which will serve as a base extraction electrode, and then the AJ2 wiring 42 is formed. In this way, as shown in FIG. 2B, an NPN bipolar transistor can be formed.According to this embodiment,
P+ type Po1y-3i film 30 serving as a base extraction electrode
b, the N+ type diffusion layer 34 which becomes the emitter, and the N+ type P
The o1y-8i layer 41a, as shown in the first diagram E,
For the laminated film pattern 29, an Afi wiring 35 and a Poly-8i which are connected to the 1-type Poly-si film 3ob of the base lead-out electrode and the N+ type diffusion layer 34 of the emitter can be formed by cell fan implantation. Emi.

The separation interval from the N+ type Po1y-3i film 41a is the first
As shown in Figure H and Figure 2 H, type 1 Poly-8i
Since it is determined by the thickness of the S102 film 31 on the film 3ob, it is possible to create a substantial fine separation between the emitter and base electrodes, and the inactive region can be kept to a minimum, reducing parasitic capacitance etc. This makes it possible to achieve higher speed and higher density transistors.

Furthermore, the separation S i02 between the emitter and base electrodes
As shown in FIG. 1F, the film 31 is formed by removing the N+ type Po1y-3t' film 30a on the active region and then oxidizing the P+ type Po1y-8i film 30b using the Si3N4 film 26 as a mask. Therefore, the N-type epitaxial layer 23 which is the active region
There is no stress on the structure, and no crystal defects are generated (an NPN transistor can be formed).

Note that although this embodiment has been described using an NPN type bipolar transistor, a PNP type bipolar transistor can also be formed by a similar method.

Moreover, although the Po1y-8t film is used as the semiconductor film in the explanation, it is needless to say that the same effect can be obtained even if a semiconductor film of amorphous silicon or the like is used.

Furthermore, although the PSG film is used as the deposited film containing impurities in the explanation, it goes without saying that similar effects can be obtained by using a deposited film such as an arsenic-doped silicon oxide film.

Effects of the Invention As described above, according to the present invention, the base extraction electrode and the emitter electrode can be formed with a fine separation interval and in a self-adhesive manner, making it possible to form high-speed, high-density bipolar transistors. A semiconductor device having the above structure can be easily manufactured with high yield.

[Brief explanation of drawings]

FIG. 1 4-(c) are NPs of the first embodiment according to the present invention.
FIGS. 2A and 2B are cross-sectional views of the manufacturing process of the N-type bipolar transistor of the second embodiment of the present invention.
3rd cross-sectional view of the manufacturing process of a PN type bipolar transistor
Figures (A) to (H) are cross-sectional views of the manufacturing process of a conventional NPN type bipolar transistor. 20... P-type Si substrate, 23... N-type shrimp layer, 30 b----P'' type Po1y-8t film, 3
1...5102 film, 33,40...P swelling diffusion layer, 34...N+ type diffusion layer, 41 a-=-
N+ type Po1y-8i film, 26...---F3iN
Membrane, 27...CvD-8iO2 membrane, 28...
...PSG film. Name of agent: Patent attorney Toshio Nakao and one other person
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Old Wari 1 Cq Castle 5 Heritsu Castle Q *0-2 Mitsu 3 Suna) Hahe Castle 1) Servant C
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Claims (1)

[Claims] (1) On one main surface of a substrate having one conductivity type semiconductor layer,
a step of forming a predetermined laminated film consisting of at least an oxidation-preventing film and a deposited film containing impurities, a step of forming a semiconductor film on the substrate, and a step of diffusing the impurity from the laminated film into a part of the semiconductor film. forming an impurity diffusion region, selectively etching the semiconductor film, and removing the semiconductor film in the impurity diffusion region where the etching rate is high;
a step of leaving a semiconductor film in a region where impurities with a slow etching rate are not diffused; a step of diffusing impurities of the other conductivity type using the laminated film as a mask to form a semiconductor film of the other conductivity type; A method for manufacturing a semiconductor device, comprising the step of oxidizing the other conductive type semiconductor film on a mask to form an insulating film. (2) The method for manufacturing a semiconductor device according to claim 1, wherein a phosphorus-doped silicon oxide film is used as the deposited film containing impurities. (3) The method for manufacturing a semiconductor device according to claim 1, wherein a polycrystalline silicon film is used as the semiconductor film. (4) The method for manufacturing a semiconductor device according to claim 1, wherein a mixed solution of nitric acid, hydrofluoric acid, and acetic acid is used in the selective etching of the semiconductor film. (5) The method for manufacturing a semiconductor device according to claim 1, wherein ion implantation is used in the impurity diffusion of the other conductivity type.