JPS6381831A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To contrive to be able to easily form a thick insulation-isolated film having a roughly flat surface by a method wherein the prescribed regions of a semiconductor substrate are etched and a shallow groove and deep grooves are formed. CONSTITUTION:The prescribed regions of a semiconductor substrate are etched in a depth of 1 mum equivalent to the amount of the thickness of an epitaxial layer 32 by dry etching using a CVD-SiO2 film 34 as a mask. Thereby, grooves 35 and 36 become deeper, a first deep groove 38 and a second deep groove 39, each having a depth of 2.5-3.5 mum, are formed, and at the same time, a shallow groove 40 of a depth of 1 mum, surrounded with the grooves 38 and 39, is formed. Moreover, by burying a CVD-SiO2 film 45 in the grooves 38-40, a groove 41 and a recessed part 42, SiO2 films 48 for element isolation are formed. In this case, as the deep first and second grooves and the shallow groove are connected to each other and the width Y of the grooves for interelement isolation is a wide one of 3-5 mum, a region having a fast etching rate is not formed on the surfaces of the SiO2 films 48. Accordingly, in the case of formation of a transistor, a recessed part is never generated in the surface of the isolation region even through a treatment is performed with a liquid containing hydrofluoric acid. Thereby, a thick insulating film can be formed without heating the semiconductor substrate. Accordingly, the parasitic capacity can be lessened.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit that can form high-density insulator isolation with small wiring parasitic capacitance.

2. Description of the Related Art Conventionally, an insulation isolation method has been proposed in which trenches are filled with a CVD5i02 film.

Bipolar LSI using the manufacturing process of the above insulation isolation method
The case of manufacturing is shown in FIGS. 4A to 4F.

An n-type buried region 2 is formed in a p-type silicon substrate 1 by diffusing hings to a diffusion depth of approximately 1 μm. Next, a 1 μm thick n
A shaped epitaxial layer 3 is formed.

A CVD-5i02 film 4 with a thickness of about 1-2 μm is formed, and the CVD-5i02 film 4 in the insulation isolation formation area is removed by photoetching.
5i02 film 4 is removed (FIG. 4A).

Next, the exposed silicon is etched using the CV D-8i02 film 4 as an etching mask to a depth of about 2
．． A groove 5 having a width of 5 to 3.5 μm and a width of 1.2 μm is formed. Then, using the CV D-5in2 film 4 as a mask, boron ions are implanted to form a channel stopper region 6 at the bottom of the groove 5 (FIG. 4B).

Next, a 5i02 film 7 having a thickness of 1.4 pm is formed at about 800° C. by thermal decomposition of 5iH2Cβ2 gas and N2o gas, and the groove 5 is filled with the 5102 film 7 (FIG. 4C).

Next, a photoresist film is applied to the surface of the substrate, and the photoresist film is removed by dry etching, leaving the photoresist film 8 in the recesses, and the surface is made flat (FIG. 4D).

Then, the photoresist film a and the SO2 film 7 are removed.
The surfaces of the isolation 5i02 film 7 and the epitaxial layer 3 are made flat (FIG. 4E).

Next, by selective oxidation, a field 5i02 film g, n+=r, with a thickness of about 0.6 μm, and a rectifier region 10. p-decade base region 11. An n+ type emitter region 12 is formed. In this case, since the etching rate of the SiO2 film 7 formed in the groove 5 by HF is high, a recess 13 is formed (FIG. 4F).

Problems to be Solved by the Invention In the above process, as shown in FIG.
When two films 7 are filled, the ratio of groove depth d to width W is d/w
When the value exceeds 1 to 2, a region 15 is formed in the 8102 film T above the trench 5 where the etching rate is high for an etching solution containing hydrofluoric acid (HF). Therefore, in the transistor formation step after surface planarization, a recess 16 is formed in the isolation region as shown in FIG. 5B, making it difficult to form a fine pattern. Moreover, even if the surface of the SiO2 film 7 and the surface of the silicon substrate 1 are flat after the isolation is formed, the entire SiO2 film 7 is etched in the subsequent process, and the silicon substrate 12L on the side surface of the isolation region is exposed. . When the side silicon substrate 1a of the isolation region is exposed in this way, there is a problem that the transistor characteristics deteriorate.

Furthermore, if the separation width W is increased, the thickness of the SiO2 film 7 must also be increased, which makes it difficult to form and planarize the SiO2 film 7.

Furthermore, as shown in FIG. 6, when a voltage is applied between the n+ collector diffusion layers 20 and 21 of the transistor, the isolation depth must be deep so that the depletion layer 22 does not touch the n+ collector diffusion layer 21. There is a problem that it must be done. Incidentally, if the separation width W is made wider, the depth of the separation does not have to be increased, but as mentioned above, the thickness of the SiO2 film 7 must be increased, which causes other problems.

Means for Solving the Problems The method of manufacturing a semiconductor integrated circuit according to the present invention includes etching a predetermined region of a semiconductor substrate to a desired depth and etching the first and second regions.
etching the semiconductor substrate between the first and second trenches and the first and second trenches to a predetermined depth at the same time, forming shallow trenches and third and fourth deep trenches; a step of forming a groove, a step of introducing an impurity for forming a diffusion layer having the same conductivity type as the semiconductor substrate into the bottoms of the shallow groove and the deep groove, and a step of forming the shallow groove and the deep groove using an anti-oxidation film as a mask. a step of selectively oxidizing the surface to form an oxide film; a step of forming an insulating film thicker than the depth of the shallow groove on the semiconductor substrate; and a step of selectively etching the insulating film to prevent the oxidation. A step of making the surface of the film and the surface of the insulating film buried in the trench substantially the same height, and by removing the anti-oxidation film, the exposed surface of the oxide film is higher than the exposed surface of the semiconductor substrate. It is characterized by

action The effect of this technical means is as follows.

In other words, there is no need to form a thick insulating film, and
Since the etching rate of the surface of the isolation insulating film after surface planarization is not increased with respect to the HF-based etching solution, the isolation region does not become recessed. Further, since the side surface of the semiconductor substrate in the isolation region is not exposed, deterioration of transistor characteristics can be prevented. Furthermore, since two deep isolation regions are formed between the collectors of adjacent transistors, the breakdown voltage between collectors and collectors can be increased without increasing the isolation depth.

EXAMPLE Hereinafter, as an example of the present invention, a method for forming an npn type bipolar transistor will be explained based on the steps of FIG.

An n0 diffusion layer 31 with a diffusion depth of 1 μm is formed on a p-type semiconductor substrate 30 of 10 to 2 Ω and 7 m in length by selective diffusion of arsenic. Thereafter, an n-type epitaxial layer 32 having a thickness of 1 μm and having a resistance of 0.6 Ω is formed. On top of that, a Si3N4 film 33 with a thickness of O-1 μm and an SiO film with a thickness of 1.2 μm are formed by CVD.
Two films 34 are formed. Then, the CVN-3i02 film 34 and the Si3N4 film 33 in the deep isolation region forming region are removed by photoetching, and the CVD-5i02 film is removed.
Using the film 34 as a mask, the epitaxial layer 32 and the semiconductor substrate 30 are etched by a dry etching technique of 1.5-2.
Grooves 35.5 μm etched and 0.8 to 1.2 μm wide.
36 (Figure 1 person).

Next, a photoresist film 37 is formed on the emitter, base, and collector regions of the transistor by photolithography (FIG. 1B).

Next, using the photoresist film 37 as a mask, CVD-3i0
2 film 34 and 5isN433 are removed. Thereafter, the photoresist film 37 is removed (FIG. 1G).

Next, using the G''i D -5i02 film 34 as a mask, dry etching is performed to 1 μm, which corresponds to the thickness of the epitaxial layer 32. As a result, the grooves 35 and 36 are deepened to a depth of 2.5 to 2.5 μm. A first deep groove 38 and a second deep groove 39 of 3.5 μm are formed, and at the same time the groove 3
A shallow groove 40 with a depth of 1 μm surrounded by 8.39 is formed. In addition, a groove 4 with a depth of 1 μm for separating the base and collector
1. A recess 42 in which the epitaxial layer 32 in the field region is removed is also formed at the same time. And CV D-
Approximately 25 keV was applied to the bottoms of the grooves and recesses using the 5i02 film 34 as a mask.

Inject 1~10X10 zonslon holons,
Forming a channel stopper diffusion layer 43 (FIG. 1D)
).

Next, after removing the CVD-SiO head 34, the Si3N4 film 33 which is an oxidation prevention film is used as a selective oxidation mask to
A 5102 film 4 is formed on the groove and recess surfaces by high-pressure oxidation at ℃.
4 is formed to a thickness of O-1 to 0.21 tm (FIG. 1E). Next, a layer 1.4 thicker than the depth of the shallow groove 40 is formed by low pressure CVD.
A total of 45 SiO2 films 45 with a thickness of 4 to 1.8 μm are formed.

and (e) a 1μ thick layer on the recess 42 using IJ technology.
A photoresist pattern 46 of m is formed. After that, when a photoresist film 47 is applied to the entire surface, the photoresist film 4
The surface of 7 becomes flat (FIG. 1F).

Next, the photoresist film 46 is etched using dry etching technology.
, 4.7 Etching is performed to the extent that the surface of the Si3N4 film 33 and the surface of the C''1D-5i02 film 45 are at the same height under the conditions that the etching rate is about the same as that of the CV D-5i02 film 45. , CvD-5i0
2 membranes 45 into grooves 38, 39, 40, 41. A SiO2 film 48 for element isolation can be filled in the recess 42. base,
5i02 membrane for collector separation 49° field 5in
Two films 50 can be formed simultaneously (FIG. 1G).

Next, the Si 3N4 film 33 is removed. As a result, the surface of the 5i02 film 44 and the SiO2 film 4B, which are more exposed than the surface of the epitaxial layer 32, 49. The surface of 50 is higher. By having such a structure,
The side surface of the semiconductor substrate in the isolation region is not exposed during post-processing (FIG. 1H).

Next, the n collector diffusion layers 51, 52. p+ base diffusion layer 53. n+ emitter diffusion layer 54. p+ type Po17Si
Hesmi pole 6ts, 5i02 membrane 56. Aj electrode 5
By forming 7.5B and 59.60, it is possible to form an npn type bipolar transistor having a structure as shown in FIG.

In the above process, the 5i0 filled in the grooves 38, 39, 40
2 film 48 has a deep groove width W of 0.8~0.
Since the width is as narrow as 1.2 .mu.m, regions 61 and 62 are formed where the etching rate is high for a hydrofluoric acid-based etching solution.

In this case, the deep first. The second groove and the shallow groove are connected, and the width Y of the element isolation groove is as wide as 3 to 5 μm, so 5i
A region where the etching rate is high is not formed on the surface of the 02 film 48.

Moreover, compared to the surface of the epitaxial layer 32, 5i0
The surfaces of the two films 44 and 48 are formed to be as high as the thickness of the Si3N4 film 33. Therefore, as shown in FIG. 1, even if a treatment with a solution containing hydrofluoric acid is performed during transistor formation, no recesses will be formed on the surface of the separation region. Moreover, the side surfaces of the epitaxial layer 32 are not exposed.

Furthermore, when a voltage is applied between the n+ collector diffusion layers 51 and 52, since the separation width Y is wide, the n+ collector diffusion layers 51 and 52.
The voltage between 52 and the depletion layer is high, and the n+ diffusion layer 31
The deep grooves 38 and 39 may be formed to such a depth that the p-channel stopper diffusion layer 43 and the p channel stopper diffusion layer 43 do not come into contact with each other.

In addition, the side surfaces of the p+ base diffusion layer 53 are made of SiO2 for isolation between elements.
2 film 48 and the base-collector separation 5i02 film 49, the base-collector capacitance can be reduced.

Furthermore, since the field 5i02 film 60 is as thick as 1 μm, the parasitic capacitance of the wiring and resistor formed on the 5i02 film So can be reduced. Moreover, the thick 5i02 film 48. Since 49°5o can be formed, arsenic in the n+ diffusion layer 31 will not diffuse into the epitaxial layer 32, resulting in a high base even if the epitaxial layer 32 is thin.

A collector-to-collector breakdown voltage can be obtained. Further, since boron in the channel stopper diffusion layer 43 is hardly diffused, high concentration boron does not come into contact with the n+ diffusion layer 31, so that the collector and substrate capacitances do not increase.

Further, by forming the SiO2 film 44 on the groove surface, the interface condition of the isolation region is improved, junction leakage can be prevented, and the dielectric breakdown voltage can be improved.

In the process shown in FIG. 1B, the photoresist pattern 37 was formed directly after the grooves 35 and 36 were formed, but after forming the photoresist film 63 on the entire surface as shown in FIG. Photoresist film 6 in 36
3 remains, and photoresist pattern 6 is formed as shown in Figure 3B.
4 may be formed. By using such a process, a pattern can be formed with higher precision.

Further, after forming the 5i02 film 45 or after surface planarization as shown in FIG.
5i02 membrane 48. The etching rate for hydrofluoric acid-based etching solutions of 49 and 50 can be slowed down.

Further, as shown in FIG. 2, when it is desired to widen the isolation width Y, by increasing the width M of the shallow isolation trench, the trench can be filled with the Si02 film without increasing the thickness of the 5i02 film 45.

Effects of the Invention As described above, according to the present invention, an insulating separation film having a substantially flat surface can be easily formed. Moreover, a thick insulating film can be formed without heating the semiconductor substrate. Therefore, parasitic capacitance can be reduced and miniaturization can be achieved, resulting in lower power consumption of semiconductor integrated circuits,
This greatly contributes to higher density.

[Brief explanation of the drawing]

FIG. 1 is a process cross-sectional view showing a method for manufacturing an npn-type bipolar transistor according to an embodiment of the present invention;
The figure is a cross-sectional view of the separation region in the same method, Figure 3A,
B is a process sectional view showing another manufacturing method for forming the same isolation region, FIGS. FIG. 6 is a cross-sectional view of a conventional isolation region when a voltage is applied between the collectors of the conventional isolation region. 38.39...deep groove, 40.41...
- Shallow groove, 42... recess, 45, 48, 49.
50...5i02 membrane. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
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ySL name, 56---5i(h)艮5Bsq, bo---A L ¥E! Figure 3 Figure 4 Figure 4 Figure 5/S 3i02 Figure 6

Claims (2)

[Claims] (1) forming first and second grooves by etching a predetermined region of the semiconductor substrate to a desired depth;
etching the semiconductor substrate between the first and second grooves and the first and second grooves simultaneously to a predetermined depth to form a shallow groove and third and fourth deep grooves; a step of introducing an impurity for forming the same conductivity type as the semiconductor substrate into the bottom of the groove; a step of selectively oxidizing the surfaces of the shallow groove and the deep groove using an oxidation prevention film as a mask to form an oxide film; forming an insulating film thicker than the depth of the shallow trench on the semiconductor substrate; and selectively etching the insulating film so that the surface of the oxidation prevention film and the surface of the insulating film buried in the trench are approximately at the same height. 1. A method for manufacturing a semiconductor integrated circuit, comprising: (2) The semiconductor integrated circuit according to claim 1, wherein the exposed surface of the oxide film is higher than the exposed surface of the semiconductor substrate by selectively etching the insulating film and then removing the antioxidant film. manufacturing method.