JPS63228750A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable fining the title device, to reduce junction capacitance and to increase working speed and lower power consumption by isolating a semiconductor film as a base leading-out electrode and a semiconductor film pattern as an emitter electrode by an oxide film and an insulating film. CONSTITUTION:An N diffusion layer 21, a P diffusion layer 22, an epitaxial layer 23 and an SiO2 film 24 are formed onto a substrate 20. An Si3N4 film 25 is shaped, and a CVD-SiO film pattern 26 is formed. The layer 23 is etched, using the pattern 26 and the film 24 as masks, and a poly Si film 27 is shaped. Boron ions are implanted to form a graft base diffusion layer 30, and the pattern 26 of an emitter region and a collector rogion is etched. The surface of the film 27 is etched to shape a clearance between the film 27 and the film 25, and an SiO2 film 29 is formed through selective oxidation, employing the film 25 as a mask. Accordingly, an oxide film providing insulated isolation by means of the fine clearance is formed in a self-alignment manner, thus reducing junction capacitance, then increasing working speed and lowering power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having characteristics of high speed and low power consumption.

In order to achieve high speed and low power consumption in conventional bipolar transistors, it is necessary to miniaturize the pattern and reduce the junction capacitance.

Therefore, in the past, polycrystalline silicon films (hereinafter referred to as polycrystalline silicon films)
By forming the pace extraction electrode with Si (denoted as Si), we aim to miniaturize the pattern and reduce the junction capacitance. For example, "Journal Op Solid State Circuit JVOI, 5C-1a.

&5. Published by the Institute of Electrical and Electronics Engineers, October 1981 (
IEEE JOURNAL OF 5OLID-9T
ATECIRCUTIS) Vol, 5C-16, As
, 0CTOBER1981) aims to realize high speed and low power consumption using the method shown in FIG. 3A-H.

In the conventional N method, first, as shown in FIG. 3A, the r diffusion layer 2 is
．． N epitaxial layer 3. P” diffusion layer 4゜8iQ2 film 6 is formed on the P type S1 substrate with non-doped po1
After forming the ySi film 6, a desired No/Dog poly
The Si film 6 is removed. Next, as shown in B, 5i3 is applied to the entire surface.
After forming N4Hx7, a SiO2 film 8 is formed on the entire surface, and a desired region of this 5lo2 film 8 is removed. Next, C
As shown in FIG. 2, boron is ion-implanted using the SlO□ film 8 as a mask to obtain a boron-doped polysilicon film 6a. Next, as shown in FIG.
Utilizing the difference in etching rate of the i film 6, the non-doped po 1 yS i film 6 with a high etching rate is etched to form a non-doped po 1 that will become an emitter electrode.
A ySi film 6 is obtained. Next, as shown in E, after removing the Si02 film 6, an S102 film 10 is formed by oxidation. At this time, a P++ diffusion layer 9 is formed.

Next, as shown in F, the Si3N4 film 7 is removed.

Furthermore, as shown in G, arsenic is ion-implanted into the non-doped po 1 yS i film 6 that will become the emitter electrode to form an arsenic-doped polyS i film 6b, and then an arsenic-doped polyS i film 12 is formed. At the same time, N
+ Form the diffusion layer 13. Next, a desired region of the S102 film is removed to open a base contact window, and then metal 14 is formed.

Problems to be Solved by the Invention However, the conventional manufacturing method shown in FIG. 3 has the following problems.

(2) It is difficult to precisely and finely form the po 1 yS i film 6b that will become the emitter electrode. In other words, the po 1 yS i film 6 which becomes the emitter electrode is etched as shown in the third diagram (the poron-doped po 1 yS i film 6a in which boron ions are implanted using the 8102 film 8 as a mask and the non-doped po 1 yS L film 6). Non-doped poly with high etching rate by utilizing the difference in rate
It is formed by etching the Si film 6. However, when forming the boron-doped po 1 yS i film 6a, 510
Also below the region of the second film 8 is a boron-doped polyS i film 6.
Become a. Therefore, it is necessary to side-etch the Si3N4 film 7 so that the non-doped polySi film 6 can be etched. In addition, non-doped polyS
In order to completely separate the i film 6, non-doped po
It is necessary to perform etching by the thickness of the lyS i film 6. Therefore, at least non-doped poly3
A side etch corresponding to the thickness of the i-film 6 is created. Therefore, 8 of the poron-doped po 17Si film 6a
102 film 8, the amount of side etching of the Si3N4 film 7, variations in the film thickness of the non-doped 7' polysilicon film 6, variations in the etching time of the non-doped po 1 ySi film 6, etc. Po
1 The amount of side etching of the Si film 6 is different. Therefore, the non-doped polySi used as the emitter electrode
The pattern size of the film 6 changes, making it difficult to form it precisely and finely.

■ Boron-doped polys as base extraction electrode
It is difficult to reduce the resistance of the i-film 6a. In other words, as shown in FIG. 3E, the boron-doped po 1 yS i film 6&
By forming the i02 film 10, approximately half of the Si film thickness of the Si02 film 10 is eaten away and becomes thinner, resulting in higher resistance. Therefore, boron-doped po 1 yS
When the film thickness is increased in order to lower the resistance of the i film 6a, as described above, the amount of side etching of the non-doped po 1 yS i film 6 under the SiO2O2O3 region increases, and the non-doped po 1 yS that becomes the emitter electrode increases. The accuracy of the pattern dimensions of the i-film 6 is reduced. At the same time, the non-doped po 1 yS i film 6 and the poron-doped po
1 The interval between the yS i films 6a becomes wider, and the P+ diffusion layer 11
There are problems with an increase in resistance and an increase in junction capacitance. Further, when the thickness of the SiO2 film 1o is made thinner in order to reduce the erosion of the boron-doped polySi film 6a due to oxidation, the insulation properties of the SiO2 film 1o become a problem.

(2) Stress is likely to occur when forming the S102 film 10. In other words, as shown in the third diagram, non-doped poll
yS i film 6 and boron-doped po 1 yS i film 6a
After separating by etching, as shown in Figure 3E (5
102 film 10, non-doped po 1 y
Since the space between the Si film 6 and the po 07 doped po 1 yS i film 6a is in the shape of a recess, stress due to oxidation is applied to the recess. In this case, the narrower the interval, the greater the stress.

Therefore, when molding with narrow intervals, defects are likely to occur due to stress, which causes a decrease in yield.

In view of these conventional problems, it is an object of the present invention to provide a method for manufacturing a semiconductor device that solves these problems and has characteristics of high speed and low power consumption.

Means for Solving the Problems The method for manufacturing a semiconductor device of the present invention includes a step of forming a thin film pattern on a semiconductor substrate on which an oxidation prevention film is formed, and a step of removing the oxide film using the thin film pattern as a mask. a step of removing the semiconductor substrate to a desired depth using the thin film pattern as a mask; a step of forming a first semiconductor film on the entire surface; and a step of removing the first semiconductor film on the thin film pattern. , removing a desired amount of the first semiconductor film, removing a desired region of the thin film pattern, and forming a multilayer film of an oxide film and an insulating film by oxidizing the first semiconductor film. a step of removing a desired region of the anti-oxidation film, a step of forming a second semiconductor film on the entire surface, and a step of forming the second semiconductor film pattern in the desired region; The method is characterized in that the first semiconductor film serving as an extraction electrode and the second semiconductor film pattern serving as an emitter electrode are separated by the oxide film and an insulating film.

For production With the above configuration, the present invention operates as follows.

■ The emitter region, graft base region, and base extraction electrode region are determined in a self-aligned manner by the thin film pattern.

■ By performing selective oxidation using the anti-oxidation film remaining on the emitter region as a mask, the area between the graft base diffusion layer and the emitter diffusion layer and between the first semiconductor film which is the base extraction electrode and the second semiconductor film which is the emitter electrode is removed. A 5i02 film that insulates and isolates patterns at minute intervals can be formed.

(2) By selectively etching the anti-oxidation film on the emitter region, a fine emitter diffusion window can be formed in a self-aligned manner.

(2) The first semiconductor film and the second semiconductor film can be formed with any desired thickness, and furthermore, the insulating film can also be formed with any desired thickness. Therefore, it is no longer necessary to form a thick oxide film that serves as an insulating separation film, and it is possible to form a first semiconductor film that serves as a base lead-out electrode with low resistance.

■ A thin film pattern can be used as a field insulating layer, resulting in a flat surface.

■ By etching the first semiconductor film by a desired amount and creating a gap between it and the anti-oxidation film on the emitter region, there is a gap between the first semiconductor film and the anti-oxidation film when selectively oxidizing the first semiconductor film. It is difficult for stress to be applied to the oxide film, and it is possible to prevent the oxide film from being quickly etched in areas where stress is applied and the insulation properties to deteriorate during subsequent cleaning or the like.

■ Graft base ′□ before forming the first semiconductor film
By etching the region semiconductor substrate, selective oxidation of the first semiconductor film can improve the oxidation shape under the anti-oxidation film, and the high concentration region and active base region under the craft base can be improved. base resistance can be reduced because they are joined at a close distance. Furthermore, the P1 diffusion layer 30 and the N+ diffusion layer 34 are less likely to come into direct contact with each other, and the capacitance can be reduced.

EXAMPLE Hereinafter, one example of the method for manufacturing a semiconductor device of the present invention will be described as a first example.
This will be explained based on FIGS. 2 and 3.

It is called A. FIG. 1 shows the case of an NPN type bipolar transistor. First, as in step A, an N+ diffusion layer 21.
P+ diffusion layer 22. epitaxial layer 23, and Sio
After forming a 513N4 film 25 as an oxidation prevention film on a P-type St substrate 2o as a semiconductor substrate formed into two films and 24 films, a CVD-8i02 film pattern 26 as a thin film pattern is formed.

After that, using this thin film pattern 26 as a mask, Si3N
4 film 25 is etched.

Next, CVD-S i 02 film pattern 26 Oyohi 5
Post-process B in which the N epitaxial layer 23 in the graft base region is etched by a desired amount using the 102 film 24 as a mask.
po 1 yS as the first semiconductor on the entire surface as in
An i film 27 is formed. Thereafter, a resist film 28 serving as an etching mask material is formed in a region other than on the thin film pattern 26, and using this resist film 28 as a mask, the polySi film 27 on the thin film pattern 2θ is etched away. Thereafter, as in step C, the resist film 28 is removed. Next, boron ions are implanted into the po 1 yS 1 film 27 to form a graft base diffusion layer, and then the thin film pattern 26 in the emitter region and collector region is etched as in step 3.

Next, the surface of the po 17S i film 27, which is the first semiconductor film, is etched to form a gap between it and the Si3N4 film 26 (see the enlarged view shown in FIG. 2A).

Thereafter, selective oxidation is performed using the Si3N4 film 25 as a mask to form a 5to2 film 29. At this time, S 1o2
N 29 f'i first semiconductor film polySi film 27
A 5L3N4 film 2 is formed on top and is an anti-oxidation film.
6 (see Figure 2B).

In addition, due to this oxidation heat treatment, boron in the polysi film 27 is diffused into the N epitaxial layer 23,
A P diffusion layer 30, which is a graft-based diffusion layer, is formed. Next, as in step E, CVD is applied as an insulating film over the entire surface.
After forming the -3iO2 film 38, a resist film pattern 39 is formed as an etching mask material. Next, as in step F, using this resist film pattern 39 as a mask, the CvD-8IQ) film 38 as an insulating film on the 813N4 film 26 as an oxidation prevention film is etched, and after etching the Sarani Si3N4 film 26. , the resist film pattern 39 is removed.

Next, as in step G, a po
A lyS i film 31 is formed. Then this poly
Boron ions are implanted into the Si film 31 to form an active base diffusion layer, and a P+ diffusion layer 32 which becomes an active base diffusion layer is formed by heat treatment.

Next, after performing arsenic ion implantation to form an emitter diffusion layer in the polysi film 31 of the second semiconductor film, as in step H, the 513N4 film 33 is used as an oxidation prevention film.
An N+ diffusion layer 34, which will become an emitter diffusion layer, is formed by heat treatment. P+ diffusion layer 32 and N+ diffusion layer 3
The formation of 3 is shown in FIG. 2C.

Next, after forming a second semiconductor film pattern 31' and a 513N4 film 33' as an anti-oxidation film pattern in the emitter region and collector region as in step I, a side surface of the second semiconductor film pattern 31' is formed by selective oxidation. 5 lo
Two films 36 are formed.

Next, the 813N4 film 33' of the oxidation prevention film pattern is removed as in step (2) to form a base contact window 36.

Next, by forming an Al wiring 37 as a metal wiring, an NPN type bipolar transistor is obtained as shown in the process.

Although the first embodiment described above uses CVD-3in2 films as the thin film pattern 26 and the insulating film 38, these are photo-CVD-8102 films.

An insulating thin film such as a plasma 5102 film may also be used.

In addition, a 513N4 film 26 was formed directly on the N epitaxial layer 23 as an anti-oxidation film, but during this time a thin S
An iO3 film may be formed in advance.

In addition, in forming the graft base diffusion layer 30, the first
As shown in FIG. This may be done by implantation or by using a doped semiconductor film.

Furthermore, the CvD-8102 film 3 which is the insulating film is
The multilayer film of No. 8 is made in the first drawing, and after performing selective oxidation as shown in E to create a 5lo2 film 29, a CVD-3in2 film 38 as an insulating film is formed on the entire surface, and a CVD-3iO□ is formed using a V cyst film pattern. Although the film 38 is formed by etching, the 5lo2 film 29 may also be formed by forming the CVD-3in2 film 38 on the entire surface, etching the CVD-8in2 film using a resist film pattern, and then performing oxidation. . Furthermore, after forming a CVD-8iQ2 film 3B on the entire surface, oxidation is performed to form a 5lo2 film 29,
The CVD-8tQ2 film 29 may be etched using a resist film pattern.

Figures 3A and 3B show a second embodiment. FIG. 3 also shows the case of an NPN type bipolar transistor, and in the first embodiment, as shown in FIG.
Although the 3N4 film 26 is formed, a 513N4 film 4o as an oxidation prevention film is formed only in the active region as shown in FIG. 2A. For example, the oxidation prevention film used as a selective oxidation mask for the sio film 24 may be left intact. After that, a thin film pattern 26 is formed, and the same steps as in FIGS. 1A to 1 are performed to form an AI wiring 37 as a metal wiring, as shown in FIG. A type bipolar transistor is obtained.

In addition, the above 1. Although the second embodiment has been explained using an NPN type bipolar transistor, a PNP type bipolar transistor can also be obtained by a similar method.

Effects of the Invention As described above, according to the method of manufacturing a semiconductor device of the present invention, the following effects can be obtained.

■ Graft base diffusion layer region and emitter region in a self-aligned manner by thin film pattern.

A first semiconductor film region that will become a pace extraction electrode is determined.

■ By performing selective oxidation using the anti-oxidation film remaining on the emitter region as a mask, the first semiconductor film, which will serve as a pace extraction electrode, and the second semiconductor film, which will serve as an emitter electrode, are insulated at minute intervals in a self-aligned manner. An oxide film can be formed.

■ By forming an insulating film on the second semiconductor film, high resistance due to oxidation of the first semiconductor film, which is a paste extraction electrode, can be prevented, and the first semiconductor film and the second semiconductor film can be formed in good condition. Can be insulated and separated.

■ The graft base diffusion layer and the emitter diffusion layer can be insulated and separated at minute intervals in a self-aligned manner without the need for mask alignment.

(2) The 5lo2 film formed on the side surface of the second semiconductor film serving as the emitter electrode can prevent metal wiring, for example, from entering the interface of AI.

■ A flat surface can be obtained by using a thin film pattern as a field insulation film.

(2) By etching the first semiconductor surface to form a gap with the oxidation prevention film and then oxidizing it, an oxide film with good insulation properties can be formed.

(2) By etching the semiconductor substrate in the graft base region, the shape of the oxide film formed under the anti-oxidation film can be improved, and the paste resistance can be lowered.

As described above, the present invention can reduce junction capacitance through insulation separation and miniaturization, and greatly contributes to high speed and low power consumption of bipolar transistors.

[Brief explanation of drawings]

FIG. 1 is a process sectional view for explaining the manufacturing method in the first embodiment of the present invention, FIG. 2 is a partially enlarged sectional view for explaining the manufacturing method in the first embodiment, and FIG. The figure is a process sectional view for explaining the manufacturing method of the second embodiment, and FIG. 4 is a process sectional view for explaining the conventional manufacturing method of an NPN type bipolar transistor. 26.4o...513N4 film [antioxidation film],
26...CVD-3in2 film pattern, 27.
...polysi film [first semiconductor film], 29.
35...5tQ2 membrane, 31...pol
ysi film [second semiconductor film], 38...-CVD-
S i 02 membrane. Name of agent: Patent attorney Toshi Nakao Haga 1 person 29
-5I02 membrane M (co
li+/++/ Fig. 1 Fig. 2 Fig. a-5, 3N, 屓 (Sunka fat stop JII) Fig. 3 Yu Fig. 4

Claims (4)

[Claims] (1) forming an antioxidant film on one main surface of a semiconductor substrate; forming a thin film pattern on the antioxidant film; and removing the antioxidant film using the thin film pattern as a mask; using the thin film pattern as a mask, removing the semiconductor substrate to a desired depth; forming a first semiconductor film on the entire surface; and removing the first semiconductor film on the thin film pattern. , removing a desired region of the thin film pattern, removing a desired amount of the first semiconductor film, and forming a multilayer film of an oxide film and an insulating film by oxidizing the first semiconductor film. a step of removing a desired region of the anti-oxidation film, a step of forming a second semiconductor film on the entire surface, and a step of forming the second semiconductor film pattern in the desired region, A method for manufacturing a semiconductor device, in which a first semiconductor film and a second semiconductor film pattern are separated by the oxide film and the insulating film. (2) A multilayer film is formed by forming an insulating film on the entire surface, removing a desired region of the insulating film, and oxidizing the first semiconductor film. A method for manufacturing a semiconductor device. (3) A multilayer film is formed by selectively oxidizing the first semiconductor film, forming an insulating film on the entire surface, and removing a desired region of the insulating film, according to claim 1. A method for manufacturing a semiconductor device. (4) The method of manufacturing a semiconductor device according to claim 1, wherein after forming the second semiconductor film pattern, an oxide film is formed on the side surface of the second semiconductor film pattern.