JPS63228753A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the damage to the surface of a substrate, and to improve characteristics by forming the region of a unified and formed N-P-N/lateral P-N-P type bipolar transistor in a self-alingnment manner, using a laminating film pattern as a mask. CONSTITUTION:An Si3N4 film 6 is shaped onto a substrate 1 to which an N<+> diffusion layer 2, a P<+> diffusion layer 3, an N epitaxial layer 4 and an SiO2 film 5 are formed, and a CVD-SiO2 film 7 is shaped. The films 7 and the films 6 in a base electrode region 8 in an N-P-N type transistor (Tr) and an emitter electrode 9 and a collector region 10 in a lateral P-N-P type Tr are etched. Laminating film patterns consisting of the films 7 and the films 6 are shaped in an emitter predetermined region 11 in the N-P-N type Tr and an activation predetermined region 12 and a field predetermined region 13 in the lateral P-N-P Tr at that time. A poly Si film 14 is formed onto the whole surface, and boron is implanted. The film 14 on the film 7 is removed through etching, employing a resist film 15 as a mask. The film 7 functions as an etching stopper in this case, and the surface of the substrate can be etched without being damaged, thus improving characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to the integration of an NPN bipolar transistor and a lateral PNP bipolar transistor, which have characteristics of high speed and low power consumption.

In conventional bipolar ICs and LSIs, it is necessary to form an NPN type bipolar transistor and a PNP type bipolar transistor due to the circuit configuration. Moreover, in order to achieve high speed and low power consumption, it is necessary to miniaturize the pattern and reduce the junction capacitance. Therefore, JOURNAL OF 5OLID-3TAT has conventionally decided to form the extraction electrode with a polycrystalline silicon film (Poly Si film).
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VOL, SC-17,45, 0CTOBER1982 Te, NPN bipolar transistor structure with base Poly Si electrode and emitter Poly! 3i
A lateral PNP bipolar transistor structure with an electrode and a collector Poly St electrode has been proposed.

Problems to be Solved by the Invention In the method of manufacturing a semiconductor device having such a structure, there are the following problems.

6) Base Po of NPN type bipolar transistor
1y St electrode, emitter of lateral PNP bipolar transistor Po1y St electrode and collector P
When forming the o1y St electrode, the Po1y formed on the emitter region of the NPN bipolar transistor and the active base region of the lateral PNP transistor is
33 It is necessary to etch the film. At this time, since the Polyst film is formed directly on the silicon substrate, it is difficult to selectively etch only the PolySi film, and there is a problem that damage to the silicon substrate surface causes deterioration of characteristics. be.

(2) When opening the emitter diffusion window of the NPN bipolar transistor, the S102 film is etched by a dry etching method, which causes damage to the silicon substrate surface, causing deterioration of characteristics.

(3) Emitter Po1y St electrode and collector Po1y of lateral PNP type bipolar transistor
! The 3102 film on the active base region between the 9i electrodes cannot be formed thickly. In other words, the SiO3 film is simultaneously formed on the emitter region of the NPN bipolar transistor and an emitter diffusion window is opened, making it impossible to increase the thickness. Therefore, when metal wiring is formed on the active base region of a lateral PNP type bipolar transistor,
There is a problem in that an inversion layer is formed on the surface of the silicon substrate, causing deterioration of characteristics. Therefore, the lateral PNP
If metal wiring cannot be formed on the active base region of a type bipolar transistor, there is a problem in that high density and high integration will be hindered.

In view of these conventional problems, the present invention provides a method for manufacturing a semiconductor device that solves these problems and can integrally form an NPN type bipolar transistor and a lateral PNP type bipolar transistor having characteristics of high speed and low power consumption. In order to solve the above-mentioned problems, the present invention includes a step of forming a first insulating film for isolation between elements in a predetermined region on one main surface of a semiconductor substrate. , forming a laminated film pattern consisting of an oxidation prevention film and a second insulating film on at least the intended emitter region of the NPN bipolar transistor and the intended active base region of the lateral PNP bipolar transistor of the semiconductor substrate; forming a semiconductor film on the semiconductor substrate; and removing the semiconductor film on the laminated film pattern to form a base electrode of an NPN bipolar transistor and an emitter electrode and a collector electrode of a lateral PNP bipolar transistor. a step of forming a semiconductor film pattern; a step of removing a second insulating film on the intended emitter region of the NPN bipolar transistor; and a step of selectively forming a third insulating film on the semiconductor film pattern; Removal of the anti-oxidation film on the intended emitter region of the NPN bipolar transistor 1 ep
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It is characterized in that an N-type bipolar transistor and an ultra-high-speed lateral PNP-type bipolar transistor are integrally formed.

Second, the laminated film pattern is formed on the intended emitter region of the NPN bipolar transistor and on the intended active base region of the lateral PNP bipolar transistor, and at the same time, it is also formed on the intended field region. do.

Thirdly, after forming the first insulating film for isolation between elements, an N-type impurity diffusion layer with a higher impurity concentration than the semiconductor substrate is formed in the region of the lateral PNP bipolar transistor planned active space of the semiconductor substrate. 0 Effects The present invention has the following effects due to the above configuration.

■ By forming a laminated film pattern consisting of an anti-oxidation film and a second insulating film on the planned emitter region of the NPN bipolar transistor and the planned active paste region of the lateral PNP bipolar transistor, the NPN
Emitter region, active base region, graft base region of bipolar transistor and active base region, emitter region of lateral PNP bipolar transistor,
The collector region can be formed in a self-aligned manner0 ■ By forming the semiconductor film after forming the laminated film pattern, the emitter region of the NPN bipolar transistor and the active paste region of the lateral PNP bipolar transistor can be formed. A semiconductor film is not formed directly on a semiconductor substrate in the area as in the past. Therefore, when removing the semiconductor film, the laminated film pattern acts as an etching stopper, so the N film can be removed without damaging the semiconductor substrate.
The semiconductor film on the intended emitter region of the PN-type bipolar transistor and on the intended active base region of the lateral PNP-type bipolar transistor can be selectively removed.

■ By removing the second insulating film on the intended emitter region of the NPN bipolar transistor and selectively oxidizing it using the oxidation prevention film remaining on the emitter region as a mask, the semiconductor that will become the base electrode of the NPN bipolar transistor is formed. A third insulating film is simultaneously formed on the surface of the film pattern, the surface of the semiconductor film pattern that will become the emitter electrode of the lateral PNP type bipolar transistor, and the surface of the semiconductor film pattern that will become the collector electrode. The base region and the emitter region can be insulated and separated at a fine interval by the third insulating film formed on the surface of the semiconductor film pattern which becomes the base electrode of this NPN type bipolar transistor.

■ By selectively etching the anti-oxidation film on the emitter region of the NPN bipolar transistor,
The emitter diffusion window can be finely opened in a self-aligned manner without damaging the surface of the semiconductor substrate.

(2) The laminated film pattern formed on the active base portion of the lateral PNP type bipolar transistor serves as an isolation insulating film between the semiconductor film pattern that will become the emitter electrode and the semiconductor film pattern that will become the collector electrode. Moreover, since the laminated film pattern is thick, even if metal wiring is formed on the active base region, there is no deterioration in characteristics as in the prior art, and high density and high integration can be achieved.

(2) By simultaneously forming a laminated film pattern on the planned field region, the semiconductor film pattern can be formed in a self-aligned manner, and a flat surface can be obtained. Furthermore, since the field insulating film can be made thicker, the wiring capacitance can be reduced.

■ By forming an N-type impurity diffusion layer with a higher impurity concentration than that of the semiconductor substrate in the planned active space region of the lateral PNP bipolar transistor, punch-through between the emitter and collector due to the reduction in base width is prevented. It can be used up to high voltages.

EXAMPLES Hereinafter, the method for manufacturing a semiconductor device of the present invention will be explained based on specific examples. 1 to 8 are manufacturing process diagrams for integrally forming an NPN type bipolar transistor and a lateral PNP type bipolar transistor according to an embodiment of the present invention.

An oxidation preventive film 813 is formed on the P type semiconductor substrate (Si substrate) 1 on which the N+ diffusion layer 2, the P diffusion layer 3, the N epitaxial layer 4, and the 5i02 film 6 as the first insulating film are formed.
After forming the N4 film 6, CVD is applied as a second insulation film.
A S102 film 7 is formed. Thereafter, the base electrode region 8 of the NPN transistor, the emitter electrode region 9 and the collector region 10 (7) of the lateral PNP transistor.
The CVD-3in2 film 7 and the Si3N4 film 6 are etched (FIG. 1).

Konotoki, a laminated film pattern consisting of CV D S 102 film 7 and Si3N4 film 6 is used as the emitter area 11 of the NPN transistor, the active pace area 12 of the lateral PNP transistor, and the field area 1 of the lateral PNP transistor.
Formed in 3.

Next, a PolySt film 14 as a first semiconductor film is formed over the entire surface. Then, by ion implantation, NPN
Base electrode region 8 and lateral PNP of type transistor
Emitter electrode region 9, collector region 1 of a type transistor
Boron is implanted into the Po1ySi@14 of each of the desired doses.

At this time, if the respective doses are different, ions are implanted using a resist mask. However, if the doses are the same, ions may be implanted into the entire surface of the PolySt film 14 without a resist mask.

Thereafter, a resist film 16 is formed only in the recesses of the space electrode region 8 of the NPN transistor and the emitter electrode region 9 and collector region 10 of the lateral PNP transistor (FIG. 2).

Next, using the resist film 15 as a mask, the PO17St film 14 on the CVD-8i02 film 7 is removed by etching. At this time, the CVD-8in2 film 7 serves as an etching stopper, and the PolySt film 14 can be selectively etched without damaging the Si substrate surface. Thereafter, the resist film 15 is removed (FIG. 3). At this time, a P''PolySi film pattern 714 doped with boron is placed in the base electrode region 8 of the NPN transistor.
A, the emitter region 9 and the collector electrode region 1o of the lateral PNP transistor are each filled with PPoly St.
IE patterns 14B and 14C remain.

Next, the C' V D S 102 film 7 on the emitter region and collector region of the NPN transistor and on the base contact region of the lateral PNP transistor is etched. After that, using the 813N4 film 6 as a selective oxidation mask, the S102 films 16A and 16, which are the third insulating films, are
B, 18C is formed (Fig. 4).

At this time, the heat treatment causes the P+ graft base diffusion layer 17 of the NPN transistor, the lateral PNP transistor P
are formed simultaneously.

Next, the Si3N4 film 6 is selectively etched using an etching solution such as hot phosphoric acid. Through this process, the 813N4 film 6 of the emitter region and collector region of the NPN transistor and the base contact region of the lateral PNP transistor can be removed without damaging the semiconductor substrate surface.
is removed, forming fine openings. Thereafter, a PO17St film 2o as a second semiconductor film is formed over the entire surface. Then, boron ions for forming an active base diffusion layer of an NPN transistor are implanted into this PolySt film 2o, and a P diffusion layer 21, which will become an active base diffusion layer, is formed by heat treatment (FIG. 5).

Next, arsenic ions are implanted into the PolySt film 2o to form an emitter diffusion layer of an NPN transistor, and then a Si3N4 film 22 is formed, and an N+ diffusion layer 23, which will become an emitter diffusion layer, is formed by heat treatment ( Figure 6). At this time, N+ diffusion layers 24 and 25 are simultaneously formed in the collector region of the NPN transistor and the base contact region of the lateral PNP transistor, respectively.

Next, an N''PolySt film pattern 2OA is applied to the emitter region and collector region of the NPN transistor and the base contact region of the lateral PNP transistor.
20B, 20C and 513N4 film patterns 22A, 2
2B and 22C are formed, respectively.

After that, Si3N4 film patterns 22A and 22B are formed.

Selective oxidation was performed using 22C as a mask, and N”PolySt
SiO3 on the sides of the film patterns 72OA, 20B, 20C
Films 26A, 26B, and 2θC are formed (FIG. 7).

Next, S13N 4 film patterns 22A and 22B.

After removing 22C, the base contact window of the NPN transistor, the emitter contact window of the lateral PNP transistor, and the collector contact window are formed. After that, if A2 wiring 2 is completed as metal wiring, NP
An N-type transistor 28 and a lateral PNP transistor 29 are integrally formed (FIG. 8).

In addition, in the above example, the 513N4 film 8 and the CV D S t 02 film 7 are also placed on the field planned area 13.
Although a laminated film pattern consisting of the above is formed, it may be applied only on the intended emitter region of the NPN transistor and the intended active paste region of the lateral PNP transistor. In this case, after etching the Po1ySt film on the laminated film pattern, the P"Po1ySi film pattern 14A is etched.
, 14B, and 14C, unnecessary portions of the Po'ly St film may be etched using a resist mask.

Furthermore, although the description has been made using a CV D S 102 film as the second insulating film, this is a photo CVD-3t○2 model.

An insulating thin film such as a plasma SiO2 film may also be used.

Also, S is added on the N epitaxial layer 4 as an oxidation preventive.
Although the L 3N 4 film 6 was directly formed, a thin S
An i02 film may be formed in advance.

Furthermore, in the above embodiment, the N epitaxial layer 4
was used as the active base layer of the lateral PNP transistor, but after forming the 5lo2 film 5, the lateral PNP
An N expansion diffusion layer having a higher impurity concentration than the N epitaxial layer 4 may be formed in the active region of the type transistor by, for example, arsenic ion implantation, and may be used as an active base layer. By doing this, the punch-through voltage between the emitter and collector can be improved, the base width can be reduced, and
It can also be used at high voltages.

Effects of the Invention As described above, according to the method of manufacturing a semiconductor device of the present invention, the following effects can be obtained.

(2) A Po1ySi film pattern can be formed without damaging the surface of the semiconductor substrate in the emitter region of the NPN transistor and the active space region of the lateral PNP transistor.

■ Emitter region and active base region of NPN transistor by forming laminated film pattern.

Graft base region, Po1ySi serving as pace electrode
Patterning region and emitter region, active base region of lateral PNP transistor.

A collector region, a Po1y Si film pattern region that becomes an emitter electrode, a Po1y Si film pattern region that becomes a collector electrode, and a field region are formed in a self-aligned manner.

■ Po1y, which becomes the base electrode of the NPN transistor
The Si layer pattern, the Po1y Si @ pattern that becomes the emitter electrode of the lateral PNP transistor, and the Po1y St film pattern that becomes the collector electrode can be formed in a self-line pattern using the same Po1y St film.

■ C V D S z 0 which becomes field insulating film
2 membranes.

The surface of the 5IO2 film on the PolySt pattern film and the CvD-8iO2 film on the active space region of the lateral PNP transistor can be formed flat.

■ By selectively oxidizing the Si3N4 film remaining on the emitter region of the NPN transistor as a mask, the first PO17, which becomes the base electrode in a self-aligned manner, is formed.
A Si film and a second PolySt serving as an emitter electrode
It is possible to form an S102 film in which the films can be insulated and separated at minute intervals.

(2) It is possible to insulate and separate the graft base diffusion layer and emitter diffusion layer of an NPN transistor at minute intervals in a self-aligned manner without mask alignment.

(2) By selectively etching the Si3N4 film remaining on the emitter region of the NPN transistor, a fine emitter diffusion window can be opened without damaging the semiconductor substrate.

■ Due to the thick layered film pattern remaining on the active base region of the lateral PNP transistor,
Gold 1 wiring can be formed on the active base region without affecting the characteristics.

■ Forming a laminated film pattern in the field area
Therefore, wiring capacitance can be reduced.

(2) By forming in the active region of the lateral PNP transistor an N-swelled diffusion layer with a concentration higher than that of the semiconductor substrate, the base width can be reduced and the transistor can be used up to a high voltage.

By forming the active base layer and emitter layer of a QNPN transistor by thermal diffusion from an ion-implanted Poly 31 film, a shallow emitter-paste diffusion layer can be formed. Furthermore, since ions are not directly implanted into the semiconductor substrate, there is no damage caused by ion implantation.

As described above, the present invention allows an NPN bipolar transistor and a lateral PNP transistor to be integrally formed, reduces junction capacitance through isolation and miniaturization, and contributes to high speed and low power consumption of bipolar ICs, I, and SI. This will make a major contribution.

[Brief explanation of the drawing]

□ FIGS. 1 to 8 are process diagrams for explaining a manufacturing method in an embodiment of the present invention. 6, 22-----・S i3N4 (oxidation prevention film)
7...CV D S 102 film (second insulating film) 14, 20...-Poly St film (semiconductor film), 5...SiO2 film (first insulating film) . Name of agent: Patent attorney Toshio Nakao and one other person
ゞ憾城qcoU) area castle

Claims (3)

[Claims] (1) A step of forming a first insulating film for isolation between elements in a predetermined region on one principal surface of a semiconductor substrate; forming a laminated film pattern consisting of an oxidation-preventing film and a second insulating film on a region where the active base of the transistor is to be formed; forming a semiconductor film on the semiconductor substrate; a step of removing the film to form each of the semiconductor film patterns that will become the base electrode of the NPN bipolar transistor, the emitter electrode and the collector electrode of the lateral PNP bipolar transistor;
a step of removing a second insulating film on the intended emitter region of the N-type bipolar transistor; a step of selectively forming a third insulating film on the semiconductor film pattern; and a step of selectively forming a third insulating film on the intended emitter region of the NPN-type bipolar transistor. A method for manufacturing a semiconductor device, comprising the step of removing an upper oxidation prevention film to open an emitter diffusion window, and forming an NPN bipolar transistor and a lateral PNP bipolar transistor in an integrated manner. (2) A patent characterized in that a laminated film pattern is formed on the intended emitter region of an NPN bipolar transistor and the intended base region of a lateral PNP bipolar transistor, and simultaneously on the intended field region. A method for manufacturing a semiconductor device according to claim 1. (3) After forming the first insulating film for isolation between elements, an N-type impurity diffusion layer with a higher impurity concentration than the semiconductor substrate is formed in the region where the active base of the lateral PNP bipolar transistor is to be formed on the semiconductor substrate. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of: