JPS60235466A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the need for an alignment margin, and to manufacture a semiconductor device having high density by forming a selective oxide film by an oxidation-resistant film, removing the oxidation-resistant film while using a film on the oxidation-resistant film as a mask and shaping an inactive base. CONSTITUTION:Oxide films 106a, 106b are formed in approximately 1,000Angstrom through selective oxidation while employing a nitride film 102 as a mask. The nitride film 102 is removed while using a CVD SiO2 film 103 as a mask, and P type inactive base regions 108a, 108b are shaped through thermal diffusion by a BSG film 17. Ions are implanted through the nitride film 102 to form an active base region 110 and an emitter 111. Consequently, the inactive base region 108b is shaped while employing the selective oxide film 106b and the over- etched CVD SiO2 film 103 as masks, thus eliminating the need for a mask alignment margin as seen in conventional devices. Accordingly, the area of a base is also reduced, and the degree of integration can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device with high density, high speed, and high precision.

Conventional configurations and their problems Semiconductor devices have recently become more and more densely packed and highly accurate.
There is a growing need for transistors with less variation in Fx. In order to meet this requirement, an inert base was formed using an insulating film and an oxidation-resistant film as a mask, and a selective acid was applied.
r'-r)-, a method of forming multiple active bases and emitters by ion implantation using a transitional ugly film as a mask for one L is shown in Japanese Patent Application No. 68-20662.
FIG. 1 shows cross-sectional views at each step.

This will be explained below with reference to FIG. For example, by thermal oxidation method on the main surface of the n-type Si substrate 1! After forming about 4,000 1lS102 films 2, providing an opening in the part that will become the base region, and forming the Si, N 4 film 3 in the part that will become the emitter region,
For example, p-type inactive base regions 4a, 4 are formed by a thermal diffusion method from galanic (hereinafter referred to as BSG) containing boron.
b (Fig. 1A). Next, by thermal oxidation, an oxide film 6 of approximately 3000 m thick is selectively formed using the nitride film 3 as a mask (FIG. 1B). Then, using the oxide films 2 and 6 as masks, the fiB 4 is implanted through the nitride film 3 by ion implantation.
1 to 3 x 10” 1ons/, 1 at 0KeY
As at 180KeV 7 x 10” 1oz/
(Do a drive of about yl. After this, 100'C
The active base region 6. is heat-treated for 30 to 60 minutes in a N2 atmosphere at a temperature of 6. An emitter region 7 is formed. At this time, defects induced by the ion implantation are incorporated into the emitter region 7 as indicated by a broken line 108 (FIG. 1C).

After that, the nitride film 3 is removed and a base contact window is opened in the oxide film 6, and the emitter electrode 9 and the base electrode 1 are opened.
0 (FIG. 1D). Note that the collector window and collector electrode are omitted here. The transistor manufactured in this manner has the following advantages.

(1) High density and high speed by self-aligning the emitter and emitter contact. ...This is because an emitter is formed under the nitride film 3 and an emitter contact window can be opened by removing the nitride film 3.

Contact margin is no longer required, allowing for higher density,
Furthermore, by making the emitter clearer, the speed can be increased.

(21 High precision... Active base 6 is improved by ion implantation)
, to form emitter vines 7, the base width can be controlled with precision, and defects induced during ion implantation are formed only within the region T that will become the emitter, and defects induced during ion implantation do not cross the pn junction. Therefore, the bare transistor has a small base-emitter voltage difference (Δ~BE) from two points of view: low leakage current.

In other words, high precision transistors can be manufactured.

However, in the above example, the nitride film 3 must be formed inside the opening portion of the oxide film 2, and an alignment margin is required. This point will become more and more dense in the future,
This will be a big challenge. Also.

In extremely highly integrated integrated circuits, it is extremely difficult to maintain a margin of 1 at both ends of the chip.

Purpose of the Invention In view of these conventional problems, the present invention provides a high-density, high-precision,
The object of the present invention is to provide a method for manufacturing a semiconductor device suitable for high speed.

Structure of the Invention The present invention forms a selective oxidation film on an oxidation-resistant film, removes the oxidation-resistant film using the film formed on the oxidation-resistant film as a mask, and forms a cine-active base by thermal diffusion. This method eliminates the need for alignment margins and allows high-density semiconductor devices to be manufactured without increasing base resistance.

Description of examples A method according to an embodiment of the present invention will be explained using the drawings.

FIG. 2 shows a process sectional view of an embodiment of the present invention, and the following description will be made according to FIG. Approximately 600 layers of nitride film 102 are formed on the main surface of the n-type substrate 1o1.

After depositing approximately 3000 VD 5102 films, a resist 104 is formed by photolithography, and then the CVDSiO2 film 103° nitride film 102 is etched vertically by dry etching or the like. (Figure 2A). Next, using the resist 104 as a mask, apply a process such as etching or etching.G V' D 5in2
Side etching of the film 103 is performed (FIG. 2B).

While removing the resist 104, a resist 106 is formed by photolithography, and the CVD 5in2 film 103 is removed using the resist 105 as a mask (second step).
Figure C). While removing the resist 105, the nitride film 1
Selectively oxidize using 02 as a mask to form an oxide film 1061a,
Approximately 1000 people will form 106b (Figure 2D). Shi VD
The nitride film 102 is removed using the 3i02 film 103 as a mask, and thermal diffusion is performed using the BSG film 107 to form p-type inactive base regions 10B&, 1081) (FIG. 2E).

The BSG film 107 and CVDSiO2 film 103 are removed. At this time, 106a and 106b are removed (although they may remain depending on the case).

After this, oxide films 109&, 109b are formed with a thickness of approximately 3000A by thermal oxidation using the nitride film 102 as a mask, and B is ion-implanted through the nitride film 102 using the oxide films 109&, 109b as a mask at θV of 1 to 3. X 1
0” 1ons/7, As at 180KeV 7X
10” Perform implantation at approximately 1 ounce/d.

After this, at a temperature of about 1000℃, in a N2 atmosphere,
A heat treatment is performed for 60 minutes to form an active base region 110 and an emitter 111. At this time, defects induced by the ion implantation are incorporated into the emitter region 111 as indicated by a broken line 112 (FIG. 2F).

At the same time as removing the nitride film 102, a base contact window is opened in the oxide film 109a, and a base electrode 113 and an emitter electrode 114 are formed (FIG. 2G).

Note that the collector window and collector electrode are also omitted here.

According to this embodiment, the inactive base region 108b is formed using the C V D 5in2 film 103 that has been over-etched with the selective oxide film 106b as a mask, so a mask alignment margin unlike the conventional method is not required. Therefore, the base area can be reduced and high integration is possible. When the emitter mask has a size of 6μ7x1x3μm, the base area is 9μmx11μm in the conventional method, whereas in this example the base area is 6μ771x9.5μm, which is approximately 59% of the beine area. It is. Furthermore, since no mask alignment margin is required, the following two advantages are provided. First, in the conventional method, the width of 4Δ differs depending on the direction due to misalignment, so the base resistance changes depending on the arrangement, whereas in the example of the present invention, it is constant, so the base resistance changes depending on the arrangement. There is very little variation, and the switching time of the transistor can be kept constant. This is effective, for example, when it is necessary to keep the speed between each comparator constant, such as in a parallel M/D converter. Second, in a large-area, highly integrated circuit, there is no need for highly accurate mask alignment at both ends of the chip. In addition, one surface can be flattened. In the conventional method, the thickness of the field oxide film 2 and the oxide film 5 on the inactive base are different, so there is a step difference between them, whereas in the example of the present invention, the field oxide film and the oxide film on the inert base are the same. The film is thick and flat.

Effects of the Invention As described above, one aspect of the present invention is to form a selective oxidation film on an oxidation-resistant film, and then manually remove the oxidation-resistant film from the film on the oxidation-resistant film to form an inert base. In addition to reducing the base area and increasing the density, variations in base resistance due to placement are extremely small, making it suitable for high integration, and one surface is flattened. The idea is to provide a method for manufacturing high-precision semiconductor devices.

[Brief explanation of the drawing]

1-D are process sectional views of a conventional semiconductor device, and FIGS. 2-2G are process sectional views of a semiconductor device according to the present invention. 106a, 106b, 109&, 109b---...
Oxide film, 103...CV D 5in2 film, 1
02...Nitride film, 1o7--18G film, 108&
, 1osb ・=-・Inert base, 110...
Active base, 111... Emitter, 112...
...Ion implantation induced defects. Name of agent: Patent attorney Toshio Nakao (1st person)
Figure 2

Claims (3)

[Claims] (1) Forming a first oxidation-resistant film on a semiconductor substrate of one conductivity type, forming a resist in a desired region, and
The first film and the oxidation-resistant film are removed using the resist as a mask, and at this time, side etching is performed so that the first film is formed on the inside of the pattern of the oxidation-resistant film. a step of removing the resist and forming a first oxide film using the oxidation-resistant film as a mask;
using the film and the first oxide film as a mask, removing the oxidation-resistant film and forming a first region of the other conductivity type by thermal diffusion; a step of forming a second oxide film using the oxide film as a mask; using the second oxide film as a mask, ion implantation is performed to form a second region of the other conductivity type, a third region of the one conductivity type, and the first region; and the second above
The area is electric Iy kit m-r 71m177m life,
-J-Z>L4d>4/Ld A-J- A method for manufacturing a semiconductor device. (2) A method for manufacturing a semiconductor device according to claim 1, comprising a bipolar transistor having a semiconductor substrate as a collector, a first region as an inactive base, a second region as an active bake, and a third region as an emitter. (3) After performing side etching of the first film, the first
3. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of removing a portion including the periphery of the film.