JPS60235464A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60235464A JPS60235464A JP9127384A JP9127384A JPS60235464A JP S60235464 A JPS60235464 A JP S60235464A JP 9127384 A JP9127384 A JP 9127384A JP 9127384 A JP9127384 A JP 9127384A JP S60235464 A JPS60235464 A JP S60235464A
- Authority
- JP
- Japan
- Prior art keywords
- film
- impurity
- forming
- polycrystalline silicon
- silicon film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000012535 impurity Substances 0.000 claims abstract description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 21
- 238000009792 diffusion process Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 239000012212 insulator Substances 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000007261 regionalization Effects 0.000 claims 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052796 boron Inorganic materials 0.000 abstract description 12
- 238000009826 distribution Methods 0.000 abstract description 7
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- 238000007493 shaping process Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に係シ、特に高速、高集
積度を目的とするバイボー２トランジスタのベース・コ
ンタクト領域の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a base contact region of a Bibo 2 transistor aimed at high speed and high integration.
バイポーラ型半導体装置において、その構造についてみ
ると基板平面に垂直刃高では、エミッタ領域、ベース領
域、高抵抗コレクタ領域、及び低抵抗コレクタ領域の４
屑構造となっておシ、これら４層が２〜３μｎ１の内に
形成されている。これに対し、水平方向でね１、エミッ
タ領域、ベース領域、ベース−コンタクト領域、コレク
タコンタクト領域、絶縁領域等が縦横数十μｍの方形の
内に形成されている。このように、水平面内で大きな領
域が必要となる理由は、それぞれの領域を写真食刻法と
拡散、酸化の組み合わせで形成している為、各領域間に
マスク目金せの余裕度が必要である事と、内部素子間配
線用のコンタクト形状が、そのコンタクト抵抗値や信頼
性の問題から小さく出来ない事にある。集積回路装置の
性能向上や、集積度向上の為には、この水平面内での素
子の専有面積をいかに小さくするかが大きな焦点となっ
ておシ、それと同時にベース・コレクタ等の寄生抵抗を
小さくする方法や、写真食刻の使用回数を少なくする方
法が色々と検討されている。その中で、専有面積を小さ
くする方法としては誘電体絶縁分離法や、エミッタｅペ
ース、コレクタ等のコンタクトを一度に形成するオール
・コンタクト方式、又、ベース・コンタクト窓から自己
整合的にエミッタを形成する方法等が、又、コンタクト
形状を小さくシ、かつ、コンタクトの信頼性を向上する
方法として多結晶シリコン膜を使用する方法等が注目さ
れている。Looking at the structure of a bipolar semiconductor device, there are four parts at a height perpendicular to the substrate plane: an emitter region, a base region, a high-resistance collector region, and a low-resistance collector region.
In a scrap structure, these four layers are formed within 2 to 3 μm. On the other hand, in the horizontal direction, the emitter region, base region, base-contact region, collector contact region, insulating region, etc. are formed within a rectangle of several tens of μm in length and width. The reason why such a large area is required in the horizontal plane is that each area is formed using a combination of photo-etching, diffusion, and oxidation, so a margin of mask metallization is required between each area. In addition, the shape of the contact for wiring between internal elements cannot be made small due to problems with contact resistance and reliability. In order to improve the performance and density of integrated circuit devices, a major focus is on how to reduce the area occupied by the elements in this horizontal plane.At the same time, it is important to reduce the parasitic resistance of the base and collector. Various methods are being considered to reduce the number of times photo engraving is used. Among these methods, methods to reduce the occupied area include dielectric insulation separation method, all-contact method in which contacts such as emitter e-pace and collector are formed at the same time, and emitter self-alignment method from base contact window. In addition, a method of forming the contact using a polycrystalline silicon film is attracting attention as a method of reducing the contact shape and improving the reliability of the contact.
第１図〜第６図は従来技術を示すもので、コンタクト部
に多結晶シリコン膜を使用し、ベース・コンタクト窓か
ら自己整合的に、写真食刻法を用いずに、ベース領域、
エミッタ領域及びエミッタコンタクト部を形成するｎｐ
ｎ型トシトランジスター来の製造方法の主たる工程の、
主たる部分の断面図を示す。1 to 6 show a conventional technique in which a polycrystalline silicon film is used for the contact portion, and the base region and contact window are self-aligned from the base contact window without using photolithography.
np forming the emitter region and emitter contact part
The main steps of the conventional manufacturing method for n-type Toshi transistors are:
A cross-sectional view of the main part is shown.
第１図はｎ型シリコン基板１１上に第１の絶縁体膜１２
（酸化膜と窒化膜の重層膜）を約１５００Ｘの膜厚で形
成し、該膜上に多結晶シリコン膜（ｐｏ−１ｙｓｉ膜）
１３を約２５００Ｘの膜厚で形成し、その上に第２の絶
縁体膜１４（酸化膜、ｐｏｌｙｓｉ膜、窒化膜等の組み
合せによる膜）を約０．７μｍの膜厚で形成した所であ
る。次に写真食刻法とリアクティブイオンエッチ等の組
み合わせによシ第２の絶縁体膜１４を部分的に除去し、
残存第２の絶縁体膜１４をアスクとして、ｐｏｌｙｓｉ
膜１３に不純物添加を行なう（第２図）。この時、不純
物添加法としてはイオン注入法を用い、注入条件として
は、不純物はボロンでエネルギー（Ｅ）は５Ｑｋｅｖ、
ドーズ量（φ）は５ Ｅ １５ ａｎ−”が適当である
。しかる後に第２の絶縁体膜１４を、等方性プラズマエ
ッチや、湿式エツチングによシ側面エツチングし、Ｐｏ
１ｙ８ｉ膜１３で、ボロンが添加されていない領域を巾
０．３μｍ程度露出させる。次に露出した、ボロンが添
加されていないＰｏ１ｙ ８ｉ膜１３を食刻し、第１の
絶縁体膜１２を露出させる。このとき食刻方法としては
ＫＯＨ系液体を用いた湿式エツチングが適している。そ
の後、順次、第２の絶縁体膜１４を除去し、露出した第
１の絶縁体膜１２を除去し、開孔１６を設け、ボロンが
添加されていないＰｏ１ｙＳｔ 膜１３を除去する（第
３図）。しかる後に、再びＰｏ１ｙＳｉ膜１７を約ａｏ
ｏｏＸの膜厚で形成し、該Ｐｏ１ｙ８ｉ膜１５からボロ
ンの拡散を生ぜしめ、Ｐｏ１ｙ８ｉ膜１７中にボロン添
加領域１８を形成すると同時に開孔１６を通してシリコ
ン基板１１中にもボロン添加領域１９を形成する（第４
図）。FIG. 1 shows a first insulating film 12 on an n-type silicon substrate 11.
(multilayer film of oxide film and nitride film) is formed with a film thickness of approximately 1500X, and a polycrystalline silicon film (po-lysi film) is formed on this film.
13 is formed with a film thickness of about 2500×, and a second insulating film 14 (a film made of a combination of oxide film, polysilicon film, nitride film, etc.) is formed on it with a film thickness of about 0.7 μm. . Next, the second insulating film 14 is partially removed by a combination of photolithography, reactive ion etching, etc.
Using the remaining second insulator film 14 as an ask, polysi
Impurities are added to the film 13 (FIG. 2). At this time, the ion implantation method was used as the impurity addition method, and the implantation conditions were that the impurity was boron, the energy (E) was 5Qkev,
An appropriate dose amount (φ) is 5 E 15 an-''. After that, the second insulating film 14 is side-etched by isotropic plasma etching or wet etching.
In the 1y8i film 13, a region to which boron is not added is exposed with a width of about 0.3 μm. Next, the exposed Poly 8i film 13 to which no boron is added is etched to expose the first insulator film 12. At this time, wet etching using a KOH liquid is suitable as an etching method. Thereafter, the second insulating film 14 is removed, the exposed first insulating film 12 is removed, an opening 16 is formed, and the PolySt film 13 to which no boron is added is removed (see FIG. 3). ). After that, the Po1ySi film 17 is again coated to a thickness of about ao
ooX film thickness, causing boron to diffuse from the Po1y8i film 15, forming a boron doped region 18 in the Po1y8i film 17, and at the same time forming a boron doped region 19 in the silicon substrate 11 through the opening 16. (4th
figure).
この時、拡散条件としては９００’Ｃ，Ｎ２．６時間程
度が適当テアシ、Ｐｏ１ｙ８１膜１７中に約０．７μｍ
され、シリコン中に約０．４μｍ拡散される。その結果
、絶縁体膜１２上＋７） Ｐｏ１ｙ ８ｉ ！ａ１７
Ｋ モ絶ｆｊ１体膜端から約０．４μｍ入った所まで拡
散される。At this time, the appropriate diffusion conditions are 900'C and N for about 2.6 hours.
and diffused into silicon to a depth of approximately 0.4 μm. As a result, on the insulating film 12 +7) Po1y 8i ! a17
K is diffused up to approximately 0.4 μm from the edge of the body's membrane.
又、シリコン中のボロン拡散領域は、拡散源であるＰｏ
１ｙ８ｉ膜１５が、開孔１６の一端に接してしか形成さ
れていない為、そのシリコン中での接合深さや濃度勾配
酸第４図に示した様に、拡散源（Ｐｏ１ｙ ８１膜１５
）から離れるに従がって浅く、又薄くなる形状を有して
いる。次にＰｏ１ｙ８ｉ膜１７でボロンを添加されてい
ない部分を食刻し、開孔２０を設ける（第５図）。次に
Ｐｏ１ｙ ８ｉ膜１８表面を熱酸化し、シリコン酸化膜
２４を約３０００Ｘの膜厚で形成する。その後に核酸化
膜２４を用いて第１の絶縁体膜を食刻し開孔２０をシリ
コン基板に至達させ、その開孔を通してシリコン基板中
にボロンを添加し活性ベース領域２１を形成する。In addition, the boron diffusion region in silicon is a diffusion source of Po.
Since the 1y8i film 15 is formed only in contact with one end of the opening 16, the junction depth in the silicon and the concentration gradient acid as shown in FIG.
) It has a shape that becomes shallower and thinner as it moves away from the surface. Next, the portion of the Po1y8i film 17 to which boron is not added is etched to form an opening 20 (FIG. 5). Next, the surface of the Poly 8i film 18 is thermally oxidized to form a silicon oxide film 24 with a thickness of about 3000×. Thereafter, the first insulator film is etched using the nuclear oxide film 24 to form an opening 20 that reaches the silicon substrate, and boron is added into the silicon substrate through the opening to form an active base region 21.
次に開孔２０を覆うＰｏ１ｙ８１膜パターン２３を形成
し、該Ｐｏ１ｙ ８ｉ膜２３を通してｎ型不純物をシ
′リコン中に添加し、エミッタ領域２２を形成する（第
６図）。これによシｎＰｎ ）ランシスターが形成され
る。Next, a Po1y81 film pattern 23 is formed to cover the opening 20, and an n-type impurity is syringed through the Po1y8i film 23.
'Add into the silicon to form the emitter region 22 (FIG. 6). This forms a run sister (nPn).
以上、従来プロセスを詳細に説明したが、この従来プロ
セスによると、シリコン中に形成されたベース・コンタ
クト領域の接合深さや、不純物濃度分布が大きく不均一
力分布をしておシ、エミッタコンタクト部に近づくにつ
れて接合が浅く、濃度が薄くなる傾向を有している。又
、ポリシリ中の不純物分布も不均一となっている。この
結果、ペース寄生抵抗は太きｌり、）ランシスター素子
の動作速度の向上を図るときの大きな欠点となっている
。又Ｐｏ１ｙ Ｓｉ膜を内部抵抗素子として使用する場
合、その安定性や再現性等に信頼できない所がある。The conventional process has been explained in detail above, but according to this conventional process, the junction depth of the base contact region formed in silicon and the impurity concentration distribution are large, and the force distribution is uneven, and the emitter contact region The junction tends to become shallower and the concentration becomes thinner as it approaches . Moreover, the impurity distribution in the polysilicon is also non-uniform. As a result, the pace parasitic resistance increases, which is a major drawback when trying to improve the operating speed of the Runsistor element. Furthermore, when a PolySi film is used as an internal resistance element, its stability and reproducibility are sometimes unreliable.
本発明はこれらの点を改善しようとするもので、前記、
従来プロセスの第５図のエミッタ用開孔を設けた後に、
不純物添加を行ないベース・コンタクト領域の接合深さ
や濃度分布を均一かつ高濃度化する。それと同時にＰｏ
１ｙ Ｓｉ膜中の不純物濃度も均一化する。この結果、
ベース寄生抵抗を大巾に小さくすることが可能となシ、
又、Ｐｏ１ｙ８ｉ膜による抵抗も任意にコントロール可
能となシ、その信頼性も向上できる。The present invention aims to improve these points, and the above-mentioned
After creating the emitter hole shown in Figure 5 in the conventional process,
Impurities are added to make the junction depth and concentration distribution of the base contact region uniform and high. At the same time Po
1y The impurity concentration in the Si film is also made uniform. As a result,
It is possible to greatly reduce the base parasitic resistance,
Furthermore, the resistance due to the Po1y8i film can be controlled arbitrarily, and its reliability can also be improved.
すなわち本発明の特徴は、半導体基板表面に絶縁体膜を
形成し、該絶縁体膜上に不純物を含む第１の多結晶シリ
コン膜を部分的に形成する１槁と、該第１の多結晶シリ
コン膜の周辺の一部に隣接してベース−コンタクト用開
孔を絶縁体膜に形成する工程と、その後に、不純物が添
加されていない第２の多結晶シリコン膜を形成する工程
と、該第１の多結晶シリコン膜から第２の多結晶シリコ
ン膜に不純物の拡散を生せしめ、不純物添加領域を形成
すると同時に、前記開孔を通して基板内に不純物添加を
行なう工程と、不純物添加領域外の第２の多結晶シリコ
ン膜を除去する工程と、残存子る第２の多結晶シリコン
膜の周辺の一部を用いてエミッタ用開孔を絶縁体膜に形
成する工程を含、む半導体装置の製造方法において、前
記第２の多結晶シリコン膜の形成前又はパターン形成後
に、前記不純物と同一の不純物を添加する工程を含む半
導体装置の製造方法にある。次に実施例によシ詳細に説
明する。 、
第７図（ａ）は従来プロセスの実施例第５図に対応する
断面図である。この後に、全面に不純物添加を行ない添
加されている不純物の補正を行ない、不純物添加領域２
５を形成する（第７図（ｂ））。拡散条件としては１０
００℃２０分程度のボロン拡散が適当であシ、最終的な
深さは０．３μｍ程度で、Ｐｏ１ｙ８ｉ膜の層抵抗値は
約１００Ω／口程度となる。以下、従来プロセスに従が
い、エミッタ領域等を形成することによシトランシスタ
ー素子が作られる。That is, the features of the present invention include forming an insulating film on the surface of a semiconductor substrate, and partially forming a first polycrystalline silicon film containing impurities on the insulating film; forming a base-contact opening in an insulating film adjacent to a portion of the periphery of the silicon film, and thereafter forming a second polycrystalline silicon film to which no impurities are added; A step of causing impurity diffusion from the first polycrystalline silicon film to the second polycrystalline silicon film to form an impurity doped region, and at the same time doping the impurity into the substrate through the opening; A semiconductor device comprising the steps of: removing the second polycrystalline silicon film; and forming an emitter hole in the insulator film using a portion of the periphery of the remaining second polycrystalline silicon film. The method of manufacturing a semiconductor device includes the step of adding an impurity same as the impurity before forming the second polycrystalline silicon film or after forming the pattern. Next, an example will be explained in detail. , FIG. 7(a) is a sectional view corresponding to FIG. 5 of the conventional process embodiment. After this, impurities are added to the entire surface to correct the added impurities, and the impurity doped region 2
5 (Fig. 7(b)). The diffusion condition is 10
It is appropriate to diffuse boron at 00° C. for about 20 minutes, and the final depth is about 0.3 μm, and the layer resistance value of the Poly8i film is about 100 Ω/hole. Thereafter, a citransistor element is manufactured by forming an emitter region and the like according to a conventional process.
以上、詳細に説明した様に、本発明によると、Ｐｏ１ｙ
Ｓｉ膜を拡散源としてベース・コンタクト用Ｐ型領域を
形成した後に、再び外方よシ、不純物添加を行なう。こ
れによシベース・コンタクト部の接合深さや、不純物濃
度分布の均一化を図シ、ペース寄生抵抗の減少を容易に
行ない、合わせてＰｏ１ｙＳｉ膜中の不純物の均一化を
行ないＰｃｙｌｙＳｉ抵抗の使用を容易とする。これに
より）ランシスター素子の特性向上が容易に可能となシ
、合わせて半導体装置の信頼性向上が期待できる。As described above in detail, according to the present invention, Po1y
After forming a P-type region for base contact using the Si film as a diffusion source, external doping is again performed. This makes it easier to make the junction depth and impurity concentration distribution of the base contact part uniform, reduce the parasitic resistance of the paste, and also make the impurities in the PolySi film more uniform, making it easier to use PcylySi resistors. shall be. As a result, it is possible to easily improve the characteristics of the Runsistor element, and at the same time, it is expected that the reliability of the semiconductor device will be improved.
第１図〜第６図は従来プロセスの主たる工程のｎｐｎ
）ランシスターのエミッターベース間の断面図を示す。
又、第７図（、） 、 （ｂ）は本発明と従来プロセス
の相違点を示す断面図である。
図中の記号は下記の事物を表わす。
１１・・・・・・ｎ型シリコン基板、１２・・・・・・
第１の絶縁体膜（シリコン酸化膜又はシリコン酸化膜と
シリコン窒化膜の二重膜）、１３．１７・・・・・・多
結晶シリコン膜（不純物添加無）、１４・・・・・・第
２の絶縁体−（シリコン酸化膜、シリコン窒化膜、多結
晶シリコン膜等の重ね合せ膜）、１５，１８．２３・・
・・・・多結晶シリコン膜（不純物添加有）、１６・・
・・・・ベース・コンタクト用開孔、１９，２１．２５
・・・・・・Ｐ型不純物添加領域、２０・・・・・・エ
ミッタ形成用の孔、２２・・・・・・エミッタ用ｎ 不
純物添加領域、２４・・・・・・シリコン酸化膜である
。Figures 1 to 6 show the main steps of the conventional process.
) shows a cross-sectional view between the emitter bases of the run sister. 7(a) and (b) are cross-sectional views showing the differences between the present invention and the conventional process. The symbols in the diagram represent the following items. 11...N-type silicon substrate, 12...
First insulator film (silicon oxide film or double film of silicon oxide film and silicon nitride film), 13.17... Polycrystalline silicon film (no impurity added), 14... Second insulator (superimposed film of silicon oxide film, silicon nitride film, polycrystalline silicon film, etc.), 15, 18.23...
...Polycrystalline silicon film (with impurity addition), 16...
...Base contact hole, 19, 21.25
...P-type impurity doped region, 20...hole for emitter formation, 22...n-type impurity doped region for emitter, 24...silicon oxide film be.
Claims (1)
純物を含む第１の多結晶シリコン膜を部分的に形成する
工程と、該第１の多結晶シリコン膜の周辺の一部に隣接
してベース・コンタクト用開孔を絶縁体膜に形成する工
程と、その後に、不純物が添加されていない第２の多結
晶シリコン膜を形成する工程と、該第１の多結晶シリコ
ン膜から第２の多結晶シリコン膜に不純物の拡散を生ぜ
しめ、不純物＠切０領域を形成すると同時に、前記開孔
を通して基板内に不純物添加を行なう工程と、不純物添
加領域外の第２の多結晶シリコン膜を除去する工程と、
残存せる該第２の多結晶シリコン膜の周辺の一部を用い
てエミッタ用開孔な絶縁体膜に形成する工程を含む半導
体装ｍ、の製造方法において、前記第２の多結晶シリコ
ン膜の形成前又はパターン形成後に、前記不純物と同一
の不純物を添加する工程を含むととを荷動とする半導体
装置の製造方法。forming an insulating film on the surface of the semiconductor substrate, partially forming a first polycrystalline silicon film containing impurities on the insulating film, and forming a part of the periphery of the first polycrystalline silicon film; a step of forming an adjacent hole for a base contact in an insulating film, a step of forming a second polycrystalline silicon film to which no impurities are added, and a step of forming a second polycrystalline silicon film from the first polycrystalline silicon film. a step of causing impurity diffusion in the second polycrystalline silicon film to form an impurity@cut region and at the same time doping the impurity into the substrate through the opening; a step of removing the film;
A method for manufacturing a semiconductor device (m) comprising a step of forming an open insulator film for an emitter using a part of the periphery of the remaining second polycrystalline silicon film, wherein the second polycrystalline silicon film is A method for manufacturing a semiconductor device, including the step of adding the same impurity as the impurity before formation or after pattern formation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9127384A JPH0636415B2 (en) | 1984-05-08 | 1984-05-08 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9127384A JPH0636415B2 (en) | 1984-05-08 | 1984-05-08 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60235464A true JPS60235464A (en) | 1985-11-22 |
| JPH0636415B2 JPH0636415B2 (en) | 1994-05-11 |
Family
ID=14021841
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9127384A Expired - Lifetime JPH0636415B2 (en) | 1984-05-08 | 1984-05-08 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0636415B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7170113B2 (en) | 2003-04-01 | 2007-01-30 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
-
1984
- 1984-05-08 JP JP9127384A patent/JPH0636415B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7170113B2 (en) | 2003-04-01 | 2007-01-30 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0636415B2 (en) | 1994-05-11 |
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