JPS6220698B2 - - Google Patents

Info

Publication number
JPS6220698B2
JPS6220698B2 JP53056303A JP5630378A JPS6220698B2 JP S6220698 B2 JPS6220698 B2 JP S6220698B2 JP 53056303 A JP53056303 A JP 53056303A JP 5630378 A JP5630378 A JP 5630378A JP S6220698 B2 JPS6220698 B2 JP S6220698B2
Authority
JP
Japan
Prior art keywords
region
insulating film
drain
film
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53056303A
Other languages
English (en)
Japanese (ja)
Other versions
JPS54147789A (en
Inventor
Tadanaka Yoneda
Kazufumi Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP5630378A priority Critical patent/JPS54147789A/ja
Priority to US06/035,236 priority patent/US4204894A/en
Publication of JPS54147789A publication Critical patent/JPS54147789A/ja
Publication of JPS6220698B2 publication Critical patent/JPS6220698B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/125—Shapes of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/191—Photoconductor image sensors
    • H10P14/6334—
    • H10P14/6342—
    • H10P14/6922—
    • H10P14/6923—
    • H10P14/6928—
    • H10P32/141—
    • H10P32/171—
    • H10P76/40—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/133—Reflow oxides and glasses

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
JP5630378A 1978-05-11 1978-05-11 Semiconductor divice and its manufacture Granted JPS54147789A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP5630378A JPS54147789A (en) 1978-05-11 1978-05-11 Semiconductor divice and its manufacture
US06/035,236 US4204894A (en) 1978-05-11 1979-05-02 Process for fabrication of semiconductors utilizing selectively etchable diffusion sources in combination with melt-flow techniques

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5630378A JPS54147789A (en) 1978-05-11 1978-05-11 Semiconductor divice and its manufacture

Publications (2)

Publication Number Publication Date
JPS54147789A JPS54147789A (en) 1979-11-19
JPS6220698B2 true JPS6220698B2 (cg-RX-API-DMAC10.html) 1987-05-08

Family

ID=13023354

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5630378A Granted JPS54147789A (en) 1978-05-11 1978-05-11 Semiconductor divice and its manufacture

Country Status (2)

Country Link
US (1) US4204894A (cg-RX-API-DMAC10.html)
JP (1) JPS54147789A (cg-RX-API-DMAC10.html)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4309224A (en) * 1978-10-06 1982-01-05 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing a semiconductor device
US4304042A (en) * 1978-11-13 1981-12-08 Xerox Corporation Self-aligned MESFETs having reduced series resistance
US4291328A (en) * 1979-06-15 1981-09-22 Texas Instruments Incorporated Interlevel insulator for integrated circuit with implanted resistor element in second-level polycrystalline silicon
FR2460037A1 (fr) * 1979-06-22 1981-01-16 Thomson Csf Procede d'auto-alignement de regions differemment dopees d'une structure de semi-conducteur
US4261772A (en) * 1979-07-06 1981-04-14 American Microsystems, Inc. Method for forming voltage-invariant capacitors for MOS type integrated circuit device utilizing oxidation and reflow techniques
US4355454A (en) * 1979-09-05 1982-10-26 Texas Instruments Incorporated Coating device with As2 -O3 -SiO2
US4299862A (en) * 1979-11-28 1981-11-10 General Motors Corporation Etching windows in thick dielectric coatings overlying semiconductor device surfaces
US5202574A (en) * 1980-05-02 1993-04-13 Texas Instruments Incorporated Semiconductor having improved interlevel conductor insulation
JPS56160050A (en) * 1980-05-14 1981-12-09 Fujitsu Ltd Semiconductor device and manufacture thereof
US4356623A (en) * 1980-09-15 1982-11-02 Texas Instruments Incorporated Fabrication of submicron semiconductor devices
JPS57113235A (en) * 1980-12-29 1982-07-14 Nec Corp Semiconductor device
US4551908A (en) * 1981-06-15 1985-11-12 Nippon Electric Co., Ltd. Process of forming electrodes and interconnections on silicon semiconductor devices
US4492717A (en) * 1981-07-27 1985-01-08 International Business Machines Corporation Method for forming a planarized integrated circuit
US4419809A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Fabrication process of sub-micrometer channel length MOSFETs
US4419810A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Self-aligned field effect transistor process
US4985373A (en) * 1982-04-23 1991-01-15 At&T Bell Laboratories Multiple insulating layer for two-level interconnected metallization in semiconductor integrated circuit structures
WO1983003923A1 (en) * 1982-04-23 1983-11-10 Western Electric Company, Inc. Semiconductor integrated circuit structures having insulated conductors
US4445270A (en) * 1982-06-21 1984-05-01 Rca Corporation Low resistance contact for high density integrated circuit
US4499653A (en) * 1983-11-03 1985-02-19 Westinghouse Electric Corp. Small dimension field effect transistor using phosphorous doped silicon glass reflow process
US4603472A (en) * 1984-04-19 1986-08-05 Siemens Aktiengesellschaft Method of making MOS FETs using silicate glass layer as gate edge masking for ion implantation
US4636822A (en) * 1984-08-27 1987-01-13 International Business Machines Corporation GaAs short channel lightly doped drain MESFET structure and fabrication
US4606114A (en) * 1984-08-29 1986-08-19 Texas Instruments Incorporated Multilevel oxide as diffusion source
US4653173A (en) * 1985-03-04 1987-03-31 Signetics Corporation Method of manufacturing an insulated gate field effect device
US5247199A (en) * 1986-01-15 1993-09-21 Harris Corporation Process for forming twin well CMOS integrated circuits
US4784965A (en) * 1986-11-04 1988-11-15 Intel Corporation Source drain doping technique
JP2565317B2 (ja) * 1986-12-03 1996-12-18 富士通株式会社 半導体装置の製造方法
JPH01123417A (ja) * 1987-11-07 1989-05-16 Mitsubishi Electric Corp 半導体装置の製造方法
US4818714A (en) * 1987-12-02 1989-04-04 Advanced Micro Devices, Inc. Method of making a high performance MOS device having LDD regions with graded junctions
US5015595A (en) * 1988-09-09 1991-05-14 Advanced Micro Devices, Inc. Method of making a high performance MOS device having both P- and N-LDD regions using single photoresist mask
US5102816A (en) * 1990-03-27 1992-04-07 Sematech, Inc. Staircase sidewall spacer for improved source/drain architecture
JPH04174541A (ja) * 1990-03-28 1992-06-22 Nec Corp 半導体集積回路及びその製造方法
DE69132695T2 (de) * 1990-05-11 2002-06-13 Koninklijke Philips Electronics N.V., Eindhoven CMOS-Verfahren mit Verwendung von zeitweilig angebrachten Siliciumnitrid-Spacern zum Herstellen von Transistoren (LDD) mit leicht dotiertem Drain
US5759869A (en) * 1991-12-31 1998-06-02 Sgs-Thomson Microelectronics, Inc. Method to imporve metal step coverage by contact reflow
US5518945A (en) * 1995-05-05 1996-05-21 International Business Machines Corporation Method of making a diffused lightly doped drain device with built in etch stop
US5976939A (en) * 1995-07-03 1999-11-02 Intel Corporation Low damage doping technique for self-aligned source and drain regions
KR19990064285A (ko) * 1995-10-04 1999-07-26 피터 엔. 데트킨 도핑된 글라스로부터의 소스/드레인의 형성
CN109216273A (zh) 2017-07-06 2019-01-15 联华电子股份有限公司 半导体结构及其制造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2040180B2 (de) * 1970-01-22 1977-08-25 Intel Corp, Mountain View, Calif. (V.St.A.) Verfahren zur verhinderung von mechanischen bruechen einer duennen, die oberflaeche eines halbleiterkoerpers ueberdeckende isolierschichten ueberziehenden elektrisch leitenden schicht
GB1503017A (en) * 1974-02-28 1978-03-08 Tokyo Shibaura Electric Co Method of manufacturing semiconductor devices
US3986903A (en) * 1974-03-13 1976-10-19 Intel Corporation Mosfet transistor and method of fabrication
JPS5946107B2 (ja) * 1975-06-04 1984-11-10 株式会社日立製作所 Ｍｉｓ型半導体装置の製造法
US4151631A (en) * 1976-09-22 1979-05-01 National Semiconductor Corporation Method of manufacturing Si gate MOS integrated circuit
US4102733A (en) * 1977-04-29 1978-07-25 International Business Machines Corporation Two and three mask process for IGFET fabrication
US4114256A (en) * 1977-06-24 1978-09-19 Bell Telephone Laboratories, Incorporated Reliable metal-to-junction contacts in large-scale-integrated devices

Also Published As

Publication number Publication date
JPS54147789A (en) 1979-11-19
US4204894A (en) 1980-05-27

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