WO1983003923A1 - Semiconductor integrated circuit structures having insulated conductors - Google Patents

Semiconductor integrated circuit structures having insulated conductors Download PDF

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Publication number
WO1983003923A1
WO1983003923A1 PCT/US1983/000493 US8300493W WO8303923A1 WO 1983003923 A1 WO1983003923 A1 WO 1983003923A1 US 8300493 W US8300493 W US 8300493W WO 8303923 A1 WO8303923 A1 WO 8303923A1
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WIPO (PCT)
Prior art keywords
phosphorus
layer
rich
level
oxide layer
Prior art date
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PCT/US1983/000493
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French (fr)
Inventor
Hyman Joseph Levinstein
William David Powell, Jr.
Ashok Kumar Sinha
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Western Electric Company, Inc.
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Publication date
Application filed by Western Electric Company, Inc. filed Critical Western Electric Company, Inc.
Publication of WO1983003923A1 publication Critical patent/WO1983003923A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates to a semiconductor integrated circuit structure comprising first level metallization and second level metallization with mutual insulation therebetween.
  • Each such level of metallization includes an array of electrically conducting strips of metal for interconnecting various electrical device elements integrated in a single crystal silicon semiconductor body.
  • different levels of metallization is meant that the corresponding metal strips of the "different levels” are located upon different insulating layers which isolate the metallization strips from one another and from the semiconductor body, and hence different levels of metallization are usually located at differing distances from the underlying semiconductor body.
  • the first level metallization is insulated from the underlying semiconductor body by a field oxide layer located in contact with the silicon body.
  • first and second level metallization be separated by a good insulating layer to prevent spurious electrical connections or "shorts" between first and second level strips, particularly in the neighborhoods of cross-overs.
  • a typical insulating layer for this purpose is formed by a chemical vapor deposited (CVD) layer of silicon dioxide, deposited after the first level metallization—but before the second level metallization—has been formed.
  • CVD chemical vapor deposited
  • Workers in the art have suspected that undesirable cracks or fissures are generated through such a silicon dioxide layer, usually at corner edges of the first level metallization strips.
  • Such cracks give rise to a problem of undesirable short-circuits of second and first level metallizations at cross-overs caused by migration of metal from the second level metallization strips through the cracks down to the first level strips.
  • This problem of short-circuits becomes especially serious in dense arrays (2 micron spacing or less design parameters) of integrated circuit device elements. Since the metal used for the first level metallization, such as aluminum, melts at temperatures below those which would be required to seal the fissures by a high temperature oxide flowing step, such a high temperature step to seal the fissure is not practical.
  • the Figure shows a cross-section view of a semiconductor integrated circuit structure in accordance with a specific embodiment of the invention.
  • phosphorus-rich silicon dioxide i.e. , Si ⁇ 2 containing over 6 percent by weight of phosphorus
  • Si ⁇ 2 containing over 6 percent by weight of phosphorus has the advantage of depositing conformally over the irregular surface contours or steps presented by the metallization strips at their edges. Further, it suppresses ion migration to the interface with the underlying field oxide, which would otherwise cause spurious inversion layers in the silicon.
  • phosphorus- rich silicon dioxide has the disadvantage of absorbing ambient moisture to form phosphoric acid which may then attack and corrode the first level metallization.
  • depositing “conformally” is meant that the thickness of the deposited layer is substantially uniform, even over regions of irregular (non-planar) topology, so that the top surface of the deposited layer has a similarly irregular topology.
  • phosphorus-poor silicon dioxide (less than about 4 percent phosphorus) as an insulating layer has the reverse set of advantages and disadvantages; i.e., it deposits non-conformally, does not suppress ion migration, and does not absorb ambient moisture.
  • insulation between first and second level metallizations in a semiconductor integrated circuit structure comprises a phosphorus-rich silicon dioxide layer located upon the first level metallization and a phosphorus-poor silicon dioxide layer located upon the phosphorus-rich silicon dioxide layer.
  • the first and second level metallization are aluminum strips for circuit interconnections
  • the phosphorus-rich and phosphorus-poor silicon dioxide layers are chemical vapor deposited (CVD) layers, the phosphorus-rich layer having been plasma planarized (smoothed by plasma etching).
  • the second level metallization can penetrate through apertures in both silicon dioxide layers to make contact with an underlying silicon semiconductor body in which the circuit is integrated.
  • these apertures are formed by anisotropic etching so as not to enlarge any cracks in the phosphorus-rich oxide layer, and a relatively thin layer of titanium nitride, for example, can optionally coat the sidewalls of the apertures to ensure further that aluminum of the second level metallization is not shorted through cracks in the phosphorus-rich oxide to the first level metallization.
  • the phosphorus-rich oxide layer ensures conformal contact with the first level
  • the phosphorus-rich layer ensures satisfactory stability against ion migration which might otherwise cause spurious inversion layers or channels at the interface of the underlying silicon body with the field oxide.
  • the phosphorus-poor oxide layer prevents moisture absorption which would otherwise produce phosphoric acid, a corrosive agent which deteriorates the conductivity of the underlying metallization. Such phosphoric acid formation would be especially deleterious in the presence of above-mentioned cracks in the phosphorus-rich oxide layer.
  • a semiconductor integrated circuit structure portion 100 comprises an essentially p-type single crystal silicon semiconductor body portion 10 having an n + -type surface zone 101 at a horizontal major surface 105 of the body.
  • a relatively thin, typically 250 8 thermally grown silicon dioxide layer 11 (“gate oxide”) coats the major surface 105 overlying the n zone 101 (except for the region of an aperture 21 in this gate oxide layer) .
  • a relatively thick, typically about 4,000 K , .thermally grown layer of silicon dioxide 12 (“field oxide”) coats the remaining portion of the surface 105, that is, the portion complementary to that coated by the gate oxide.
  • a first level metallization strip 13 of aluminum typically about 7,000 ⁇ thick and about 2 micron wide as formed by selective masking and etching of a physically deposited (evaporation or sputtering) aluminum layer, overlies a portion of the field oxide layer 12.
  • phosphorus-rich silicon dioxide is meant an oxide layer containing at least about 6 percent by weight of phosphorus. Typically, however, the
  • a pair of fissures 42 and 43 may undesirably propagate from corner edge surfaces of the first level strip 13 as shown. More specifically, the fissures 42 and 43 typically extend along directions of about 45 degrees with respect to the horizontal to a sidewall of the aperture 21 (at the level of the oxide layer 14) and thence to the top surface of the phosphorus- rich oxide layer 14.
  • the phosphorus-rich oxide layer 14 has an aperture 22 (down to the top surface of the first level strip 13) in addition to the aperture 21, to enable interconnection of the first level strip 13 with a second level metallization strip 162.
  • a phosphorus-poor oxide layer 15 having a thickness of typically about 5,000 R .
  • the structure 100 includes second level metallization strips 161, 162, and 163, typically of aluminum having a thickness of about 12,000 &. These second level strips (as was the first level strip 13) are typically formed by a physical deposition process as evaporation or sputtering and patterned by selective masking and dry reactive sputter etching.
  • the aperture 21 extends through both oxide layers 15 and 14 as well as through the gate oxide layer 11 down to the n zone 101.
  • a useful sequence of steps to fabricate the structure 100 includes first forming the thick field oxide layer 12 over a limited portion of the surface 105, thermally growing the thin gate oxide layer 11, and then forming the zone 101 by introduction of impurities, as by ion implantation using the thick field oxide as a protective mask against introduction of the impurities. Then the first level metallization strip 13 is formed by a physical deposition process followed by masking and etching.
  • this first level strip is formed at a time before the aperture 21 in the gate oxide 11 exists. It is preferred that this first level metallization does not comprise polycrystalline silicon or any other material that is susceptible of being etched by the same process used for etching either the gate oxide 11, the phosphorus-rich oxide layer 14, or the phosphorus-poor oxide layer 15—lest the first level metallization be undesirably etched during the etching of apertures 21 and 22.
  • a phosphorus-rich oxide layer is deposited by a CVD step involving typically the chemical reaction of SiH ⁇ and PH3 with oxygen at a pressure of about 1.0 torr and temperature of about 440°C, and subsequently this deposited oxide layer is plasma planarized to form the phosphorus—rich oxide layer 14 with a planar top surface.
  • Fissures 42 and 43 may develop in the layer 14 during deposition, because of the sharp corner edges of the first level metallization at its interface with the field oxide 12. These fissures remain after plasma planarization.
  • planarization of this oxide layer 14 can be achieved by first depositing a phosphorus—rich oxide layer with a thickness well in excess of the ultimately desired value, and then depositing a thick, smooth-topped sacrificial layer (typically of polymer or spun-on resist) thereon characterized by an etch rate substantially equal to that of the phosphorus-rich oxide and of sufficient thickness to have a top surface which is substantially planar, and then plasma etching with a mixture of CF 4 and about 8 percent by volume of oxygen, for example, at about 50 to 60°C in order to remove entirely the sacrificial layer—all as described more fully by A. C. Adams in
  • the phosphorus-poor oxide layer 15 is deposited, typically by a low pressure (at or below about 1.0 mm Hg) CVD step involving the chemical reaction of SiH 4 with oxygen at a temperature of about 440°C. Then the apertures 21 and 22 are opened, through the oxide
  • a thin layer of sealant such as titanium nitride optionally may then be applied to seal such fissures as fissure 42.
  • This sealant is believed not to be essential in many applications because of the formation, during the etching of the aperture 21, of an insulating polymer—for example, of silicon-carbide-fluoride-oxide—which seals the fissure 42.
  • an insulating polymer for example, of silicon-carbide-fluoride-oxide—which seals the fissure 42.
  • a second level metallization of aluminum is formed in a pattern of second level metallization strips 161, 162, 163 on the top of the structure 100, as by conventional techniques of physical deposition followed by selective masking and etching.
  • the strip 161 is isolated from the fissure 43, and hence insulated from the first level strip 13, by the phosphorus-poor oxide layer 15.
  • This oxide layer 15, it should be noted, is deposited over a planarized surface of the phosphorus-rich oxide layer 14, and therefore presents a desirably smooth (planar) surface for deposition thereon of the second level metallization.
  • CHF3 for etching the aperture
  • other anisotropic reactive ion etchants of silicon dioxide can be used, such as a mixture of CHF3 and NH 3 , or of CHF3 and 0 2 or of CHF3 and C0 .
  • other sealants can be used, such as molybdenum.
  • the metal strip 162 can penetrate through an aperture (not shown) in the field oxide layer 12 to make contact with the major surface 105.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

Insulation between first and second levels of aluminum metallization in semiconductor integrated circuit structures comprises a phosphorus-rich, plasma planarized, deposited silicon dioxide layer (14) and a phosphorus-poor layer of silicon dioxide (15) deposited upon said phosphorus-rich layer.

Description

SEMICONDUCTOR INTEGRATED CIRCUIT STRUCTURES HAVING INSULATED CONDUCTORS
This invention relates to a semiconductor integrated circuit structure comprising first level metallization and second level metallization with mutual insulation therebetween.
Semiconductor integrated circuit structures, especially those having a minimum feature size of about 2 micron or less (2 micron or less design rules) , often use two different levels of aluminum metallization. Each such level of metallization includes an array of electrically conducting strips of metal for interconnecting various electrical device elements integrated in a single crystal silicon semiconductor body. By "different levels" of metallization is meant that the corresponding metal strips of the "different levels" are located upon different insulating layers which isolate the metallization strips from one another and from the semiconductor body, and hence different levels of metallization are usually located at differing distances from the underlying semiconductor body. Typically the first level metallization is insulated from the underlying semiconductor body by a field oxide layer located in contact with the silicon body. The metallization strips on different levels, however, ordinarily run at right angles to each other, whereby cross-overs occur at the resulting cross-points or intersections of second level strips with respect to first level strips. It is important that this first and second level metallization be separated by a good insulating layer to prevent spurious electrical connections or "shorts" between first and second level strips, particularly in the neighborhoods of cross-overs.
A typical insulating layer for this purpose is formed by a chemical vapor deposited (CVD) layer of silicon dioxide, deposited after the first level metallization—but before the second level metallization—has been formed. Workers in the art, however, have suspected that undesirable cracks or fissures are generated through such a silicon dioxide layer, usually at corner edges of the first level metallization strips. Such cracks give rise to a problem of undesirable short-circuits of second and first level metallizations at cross-overs caused by migration of metal from the second level metallization strips through the cracks down to the first level strips. This problem of short-circuits becomes especially serious in dense arrays (2 micron spacing or less design parameters) of integrated circuit device elements. Since the metal used for the first level metallization, such as aluminum, melts at temperatures below those which would be required to seal the fissures by a high temperature oxide flowing step, such a high temperature step to seal the fissure is not practical.
In accordance with the invention these problems are solved in an integrated circuit structure as described above characterized in that the insulation comprises a phosphorus-rich silicon dioxide layer and a phosphorus-poor silicon dioxide layer located on said phosphorus-rich layer.
In the drawing, the Figure shows a cross-section view of a semiconductor integrated circuit structure in accordance with a specific embodiment of the invention.
Only for the sake of clarity, the drawing is not to any scale.
It can be shown that phosphorus-rich silicon dioxide (i.e. , Siθ2 containing over 6 percent by weight of phosphorus) has the advantage of depositing conformally over the irregular surface contours or steps presented by the metallization strips at their edges. Further, it suppresses ion migration to the interface with the underlying field oxide, which would otherwise cause spurious inversion layers in the silicon. But phosphorus- rich silicon dioxide has the disadvantage of absorbing ambient moisture to form phosphoric acid which may then attack and corrode the first level metallization. By depositing "conformally" is meant that the thickness of the deposited layer is substantially uniform, even over regions of irregular (non-planar) topology, so that the top surface of the deposited layer has a similarly irregular topology. On the other hand, phosphorus-poor silicon dioxide (less than about 4 percent phosphorus) as an insulating layer has the reverse set of advantages and disadvantages; i.e., it deposits non-conformally, does not suppress ion migration, and does not absorb ambient moisture.
In accordance with the invention, insulation between first and second level metallizations in a semiconductor integrated circuit structure comprises a phosphorus-rich silicon dioxide layer located upon the first level metallization and a phosphorus-poor silicon dioxide layer located upon the phosphorus-rich silicon dioxide layer.
In a specific embodiment, the first and second level metallization are aluminum strips for circuit interconnections, the phosphorus-rich and phosphorus-poor silicon dioxide layers are chemical vapor deposited (CVD) layers, the phosphorus-rich layer having been plasma planarized (smoothed by plasma etching). Moreover, the second level metallization can penetrate through apertures in both silicon dioxide layers to make contact with an underlying silicon semiconductor body in which the circuit is integrated. Advantageously, these apertures are formed by anisotropic etching so as not to enlarge any cracks in the phosphorus-rich oxide layer, and a relatively thin layer of titanium nitride, for example, can optionally coat the sidewalls of the apertures to ensure further that aluminum of the second level metallization is not shorted through cracks in the phosphorus-rich oxide to the first level metallization.
In this way, the phosphorus-rich oxide layer ensures conformal contact with the first level
O PI metallization, as well as a satisfactorily ion-free quality of interface of this oxide layer with underlying field oxide; that is, the phosphorus-rich layer ensures satisfactory stability against ion migration which might otherwise cause spurious inversion layers or channels at the interface of the underlying silicon body with the field oxide. The phosphorus-poor oxide layer on the other hand prevents moisture absorption which would otherwise produce phosphoric acid, a corrosive agent which deteriorates the conductivity of the underlying metallization. Such phosphoric acid formation would be especially deleterious in the presence of above-mentioned cracks in the phosphorus-rich oxide layer.
As shown in the Figure, a semiconductor integrated circuit structure portion 100 comprises an essentially p-type single crystal silicon semiconductor body portion 10 having an n+-type surface zone 101 at a horizontal major surface 105 of the body. A relatively thin, typically 250 8, thermally grown silicon dioxide layer 11 ("gate oxide") coats the major surface 105 overlying the n zone 101 (except for the region of an aperture 21 in this gate oxide layer) . A relatively thick, typically about 4,000 K , .thermally grown layer of silicon dioxide 12 ("field oxide") coats the remaining portion of the surface 105, that is, the portion complementary to that coated by the gate oxide. A first level metallization strip 13 of aluminum, typically about 7,000 Α thick and about 2 micron wide as formed by selective masking and etching of a physically deposited (evaporation or sputtering) aluminum layer, overlies a portion of the field oxide layer 12. A plasma planarized CVD deposited layer of phosphorus-rich silicon dioxide 14, typically about 10,000 Α thick, overlies exposed surfaces of the gate oxide 11, the field oxide 12 and the first level metallization strip 13. By "phosphorus-rich" silicon dioxide is meant an oxide layer containing at least about 6 percent by weight of phosphorus. Typically, however, the
OMPI . WIPO phosphorus content is kept below about 8 percent.
Illustratively, a pair of fissures 42 and 43 may undesirably propagate from corner edge surfaces of the first level strip 13 as shown. More specifically, the fissures 42 and 43 typically extend along directions of about 45 degrees with respect to the horizontal to a sidewall of the aperture 21 (at the level of the oxide layer 14) and thence to the top surface of the phosphorus- rich oxide layer 14. The phosphorus-rich oxide layer 14 has an aperture 22 (down to the top surface of the first level strip 13) in addition to the aperture 21, to enable interconnection of the first level strip 13 with a second level metallization strip 162. Upon the phosphorus-rich oxide layer 14 is located a phosphorus-poor oxide layer 15 having a thickness of typically about 5,000 R . By "phosphorus-poor" is meant a phosphorus content in the approximate range of 0 to 4 percent. Finally, the structure 100 includes second level metallization strips 161, 162, and 163, typically of aluminum having a thickness of about 12,000 &. These second level strips (as was the first level strip 13) are typically formed by a physical deposition process as evaporation or sputtering and patterned by selective masking and dry reactive sputter etching. The aperture 21 extends through both oxide layers 15 and 14 as well as through the gate oxide layer 11 down to the n zone 101.
A useful sequence of steps to fabricate the structure 100 includes first forming the thick field oxide layer 12 over a limited portion of the surface 105, thermally growing the thin gate oxide layer 11, and then forming the zone 101 by introduction of impurities, as by ion implantation using the thick field oxide as a protective mask against introduction of the impurities. Then the first level metallization strip 13 is formed by a physical deposition process followed by masking and etching. (This first level strip is formed at a time before the aperture 21 in the gate oxide 11 exists.) It is preferred that this first level metallization does not comprise polycrystalline silicon or any other material that is susceptible of being etched by the same process used for etching either the gate oxide 11, the phosphorus-rich oxide layer 14, or the phosphorus-poor oxide layer 15—lest the first level metallization be undesirably etched during the etching of apertures 21 and 22.
Then a phosphorus-rich oxide layer is deposited by a CVD step involving typically the chemical reaction of SiH^ and PH3 with oxygen at a pressure of about 1.0 torr and temperature of about 440°C, and subsequently this deposited oxide layer is plasma planarized to form the phosphorus—rich oxide layer 14 with a planar top surface. Fissures 42 and 43 may develop in the layer 14 during deposition, because of the sharp corner edges of the first level metallization at its interface with the field oxide 12. These fissures remain after plasma planarization. The planarization of this oxide layer 14 can be achieved by first depositing a phosphorus—rich oxide layer with a thickness well in excess of the ultimately desired value, and then depositing a thick, smooth-topped sacrificial layer (typically of polymer or spun-on resist) thereon characterized by an etch rate substantially equal to that of the phosphorus-rich oxide and of sufficient thickness to have a top surface which is substantially planar, and then plasma etching with a mixture of CF4 and about 8 percent by volume of oxygen, for example, at about 50 to 60°C in order to remove entirely the sacrificial layer—all as described more fully by A. C. Adams in
"Plasma Planarization," Solid State Technology, Vol. 24, pp. 178-181 (April 1981).
Next the phosphorus-poor oxide layer 15 is deposited, typically by a low pressure (at or below about 1.0 mm Hg) CVD step involving the chemical reaction of SiH4 with oxygen at a temperature of about 440°C. Then the apertures 21 and 22 are opened, through the oxide
OMP. layers 15, 14, and 11 for the aperture 21 and through the oxide layers 15 and 14 for the aperture 22. For opening these apertures, an anisotropic etching process should be used, in order not to enlarge the fissure 42. That is, a physical process—such as reactive ion etching with CHF3— should be used. Steep sidewalls of the apertures 42 and 43 thus result.
A thin layer of sealant, such as titanium nitride optionally may then be applied to seal such fissures as fissure 42. This sealant is believed not to be essential in many applications because of the formation, during the etching of the aperture 21, of an insulating polymer—for example, of silicon-carbide-fluoride-oxide—which seals the fissure 42. Moreover, in many integrated circuits there are statistically significantly fewer opportunities for fissures to be present (of the kind formed by the fissure 42) running to the sidewalls of apertures than for fissures (like fissure 43) to be present running to the interface of the oxide layers 14 and 15, and hence there is a smaller failure probability occasioned by the fissure 42 than by the fissure 43.
Finally, a second level metallization of aluminum is formed in a pattern of second level metallization strips 161, 162, 163 on the top of the structure 100, as by conventional techniques of physical deposition followed by selective masking and etching.
Notice how, for example, the strip 161 is isolated from the fissure 43, and hence insulated from the first level strip 13, by the phosphorus-poor oxide layer 15. This oxide layer 15, it should be noted, is deposited over a planarized surface of the phosphorus-rich oxide layer 14, and therefore presents a desirably smooth (planar) surface for deposition thereon of the second level metallization. Although the invention has been described in terms of a specific embodiment, various modi ications can be made without departing from the scope of the invention. For example, instead of using CHF3 for etching the aperture, other anisotropic reactive ion etchants of silicon dioxide can be used, such as a mixture of CHF3 and NH3, or of CHF3 and 02 or of CHF3 and C0 . Instead of titanium nitride for sealing the fissure 42, other sealants can be used, such as molybdenum. It should be obvious that the metal strip 162 can penetrate through an aperture (not shown) in the field oxide layer 12 to make contact with the major surface 105.

Claims

Claims
1. A semiconductor integrated circuit structure (100) comprising first level metallization (13) and second level metallization (161) with mutual insulation therebetween
CHARACTERIZED IN THAT the insulation comprises a phosphorus-rich silicon dioxide layer (14) and a phosphorus-poor silicon dioxide layer (15) located on said phosphorus-rich layer.
2. The structure of claim 1
FURTHER CHARACTERIZED IN THAT said structure includes a semiconductor body (10) of single crystal silicon, and said first and said second level metallizations are both essentially of aluminum.
3. The structure of claim 1 FURTHER CHARACTERIZED IN THAT said first level metallization is separated from said semiconductor body by a field oxide layer, said phosphorus-rich layer is a planarized layer, and said phosphorus-poor layer is a chemical vapor deposited layer.
4. The structure of claim 1, 2 or 3 FURTHER CHARACTERIZED IN THAT a strip of said second level metallization contacts a strip of said first level metallization through an anisotropically etched aperture penetrating both said phosphorus-poor and said phosphorus-rich layers.
5. The structure of claim 1 FURTHER CHARACTERIZED IN THAT said phosphorus-rich oxide layer contains at least about 6 percent phosphorus and said phosphorus-poor oxide layer contains less than about 4 percent phosphorus.
PCT/US1983/000493 1982-04-23 1983-04-07 Semiconductor integrated circuit structures having insulated conductors WO1983003923A1 (en)

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US37105582A 1982-04-23 1982-04-23
US371,055 1982-04-23

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EP0155699A2 (en) * 1984-03-23 1985-09-25 Nec Corporation Semiconductor device having improved multi-layer structure of insulating film and conductive film
EP0359202A1 (en) * 1988-09-13 1990-03-21 Kabushiki Kaisha Toshiba Compound semiconductor device having phosphorus-containing surface protective film and method of fabricating same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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US4654269A (en) * 1985-06-21 1987-03-31 Fairchild Camera & Instrument Corp. Stress relieved intermediate insulating layer for multilayer metalization
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IT1170132B (en) 1987-06-03
EP0105915A1 (en) 1984-04-25
ES521708A0 (en) 1984-04-01
IT8320700A0 (en) 1983-04-20
GB8310669D0 (en) 1983-05-25
ES8403666A1 (en) 1984-04-01
GB2118777A (en) 1983-11-02

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