IT1170132B - SEMICONDUCTOR INTEGRATED CIRCUIT STRUCTURE WITH INSULATED CONDUCTORS - Google Patents

SEMICONDUCTOR INTEGRATED CIRCUIT STRUCTURE WITH INSULATED CONDUCTORS

Info

Publication number
IT1170132B
IT1170132B IT20700/83A IT2070083A IT1170132B IT 1170132 B IT1170132 B IT 1170132B IT 20700/83 A IT20700/83 A IT 20700/83A IT 2070083 A IT2070083 A IT 2070083A IT 1170132 B IT1170132 B IT 1170132B
Authority
IT
Italy
Prior art keywords
integrated circuit
semiconductor integrated
circuit structure
insulated conductors
conductors
Prior art date
Application number
IT20700/83A
Other languages
Italian (it)
Other versions
IT8320700A0 (en
Inventor
Hyman Joseph Levinstein
Jr William David Powell
Kumar Sinha Ashok
Original Assignee
Western Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co filed Critical Western Electric Co
Publication of IT8320700A0 publication Critical patent/IT8320700A0/en
Application granted granted Critical
Publication of IT1170132B publication Critical patent/IT1170132B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
IT20700/83A 1982-04-23 1983-04-20 SEMICONDUCTOR INTEGRATED CIRCUIT STRUCTURE WITH INSULATED CONDUCTORS IT1170132B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US37105582A 1982-04-23 1982-04-23

Publications (2)

Publication Number Publication Date
IT8320700A0 IT8320700A0 (en) 1983-04-20
IT1170132B true IT1170132B (en) 1987-06-03

Family

ID=23462292

Family Applications (1)

Application Number Title Priority Date Filing Date
IT20700/83A IT1170132B (en) 1982-04-23 1983-04-20 SEMICONDUCTOR INTEGRATED CIRCUIT STRUCTURE WITH INSULATED CONDUCTORS

Country Status (5)

Country Link
EP (1) EP0105915A1 (en)
ES (1) ES8403666A1 (en)
GB (1) GB2118777A (en)
IT (1) IT1170132B (en)
WO (1) WO1983003923A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60198847A (en) * 1984-03-23 1985-10-08 Nec Corp Semiconductor device and manufacture thereof
FR2583220B1 (en) * 1985-06-11 1987-08-07 Thomson Csf PROCESS FOR PRODUCING AT LEAST TWO METALLIZATIONS OF A SEMICONDUCTOR COMPONENT COVERED WITH A DIELECTRIC LAYER AND COMPONENT OBTAINED BY THIS DIELECTRIC
US4654269A (en) * 1985-06-21 1987-03-31 Fairchild Camera & Instrument Corp. Stress relieved intermediate insulating layer for multilayer metalization
JPH088265B2 (en) * 1988-09-13 1996-01-29 株式会社東芝 Compound semiconductor device and manufacturing method thereof
US5424570A (en) * 1992-01-31 1995-06-13 Sgs-Thomson Microelectronics, Inc. Contact structure for improving photoresist adhesion on a dielectric layer

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3882530A (en) * 1971-12-09 1975-05-06 Us Government Radiation hardening of mos devices by boron
US4005455A (en) * 1974-08-21 1977-01-25 Intel Corporation Corrosive resistant semiconductor interconnect pad
JPS5171068A (en) * 1974-12-16 1976-06-19 Matsushita Electronics Corp HANDOTA ISOCHI
JPS54147789A (en) * 1978-05-11 1979-11-19 Matsushita Electric Ind Co Ltd Semiconductor divice and its manufacture
JPS577153A (en) * 1980-06-16 1982-01-14 Nec Corp Preparation of semiconductor device
JPS6046546B2 (en) * 1980-06-16 1985-10-16 日本電気株式会社 Manufacturing method of semiconductor device
JPS5727047A (en) * 1980-07-25 1982-02-13 Seiko Epson Corp Semiconductor device
JPS57113235A (en) * 1980-12-29 1982-07-14 Nec Corp Semiconductor device

Also Published As

Publication number Publication date
EP0105915A1 (en) 1984-04-25
ES521708A0 (en) 1984-04-01
IT8320700A0 (en) 1983-04-20
GB8310669D0 (en) 1983-05-25
WO1983003923A1 (en) 1983-11-10
ES8403666A1 (en) 1984-04-01
GB2118777A (en) 1983-11-02

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