GB2118777A - Insulation layer between metallization in a semiconductor integrated circuit structure - Google Patents

Insulation layer between metallization in a semiconductor integrated circuit structure Download PDF

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Publication number
GB2118777A
GB2118777A GB08310669A GB8310669A GB2118777A GB 2118777 A GB2118777 A GB 2118777A GB 08310669 A GB08310669 A GB 08310669A GB 8310669 A GB8310669 A GB 8310669A GB 2118777 A GB2118777 A GB 2118777A
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United Kingdom
Prior art keywords
phosphorus
layer
rich
metallization
level
Prior art date
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GB08310669A
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GB8310669D0 (en
Inventor
Hyman Joseph Levinstein
William David Powell
Ashok Kumar Sinha
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AT&T Corp
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Western Electric Co Inc
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Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of GB8310669D0 publication Critical patent/GB8310669D0/en
Publication of GB2118777A publication Critical patent/GB2118777A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

Insulation between first and second levels of aluminum metallization in semiconductor integrated circuit structures comprises a phosphorus-rich, plasma planarized, deposited silicon dioxide layer (14) and a phosphorus-poor layer of silicon dioxide (15) deposited upon said phosphorus-rich layer.

Description

SPECIFICATION Semiconductor integrated circuit structure This invention relates to semiconductor integrated circuit structures including first level metallization and second level metallization with mutual insulation therebetween.
Semiconductor integrated circuit structures, especially those having a minimum feature size of about 2 micron or less (2 micron or less design rules), often use two different levels of aluminium metallization. Each such level of metallization includes an array of electrically conducting strips of metal for interconnecting various electrical device elements integrated in a single crystal silicon semiconductor body. By "different levels" of metallization is meant that the corresponding metal strips of the "different levels" are located upon different insluating layers which isolate the metallization strips from one another and from the semiconductor body, and hence different levels of metallization are usually located at differing distances from the underlying semiconductor body.Typically the first level of metallization is insulated from the underlying semiconductor body by a field oxide layer located in contact with the silicon body. The metallization strips on different levels, however, ordinarily run at right angles to each other, whereby cross-overs occur at the resulting cross-points or intersections of second level strips with respect to first level strips. It is important that this first and second level metallization be separated by a good insulating layer to prevent spurious electrical connections or "shorts" between first and second level strips, particuarly in the neighbourhoods of cross-overs.
A typical insulating layer for this purpose is formed by a chemical vapour deposited (CVD) layer of silicon dioxide, deposited after the first level metallization-but before the second level metallization-has been formed. Workers in the art, however, have suspected that undesirable cracks or fissures are generated through such a silicon dioxide layer, usually at corner edges of the first level metallization strips. Such cracks give rise to a problem of undesirable short-circuits of second and first level metallizations at crossovers caused by migration of metal from the second level metallization strips through the cracks down to the first level strips. This problem of short-circuits becomes especially serious in dense arrays (2 micron spacing or less design parameters) of integrated circuit device elements.
Since the metal used for the first level metallization, such as aluminium, melts at temperatures below those which would be required to seal the fissures by a high temperature oxide flowing step, such a high temperature step to seal the fissure is not practical.
In the invention as claimed the insulation comprises a phosphorus-rich silicon dioxide layer and a phosphorus-poor silicon dioxide layer located on the phosphorus-rich layer.
It can be shown that phosphorus-rich silicon dioxide (i.e., SiO3 containing over 6 percent by weight of phosphorus) has the advantage of depositing conformally over the irregular surface contours or steps presented by the metallization strips at their edges. Further, it suppresses ion migration to the interface with the underlying field oxide, which would otherwise cause spurious inversion layers in the silicon. But phosphorus-rich silicon dioxide has the disadvantage of absorbing ambient moisture to form phosphoric acid which may then attack and corrode the first level metallization. By depositing "conformally" is meant that the thickness of the deposited layer is substantially uniform, even over irregular (nonplanar) regions, so that the top surface of the deposited layer is similarly irregular.On the other hand, phosphorus-poor silicon dioxide (less than about 4 percent phosphorus) as an insulating layer has the reverse set of advantages and disadvantages; i.e., it deposits non-conformally, does not suppress ion migration, and does not absorb ambient moisture.
In a specific embodiment of the invention, the first and second level of metallizations are aluminium strips for circuit interconnections, the phosphorus-rich and phosphorus-poor silicon dioxide layers are chemical vapour deposited (CVD) layers, the phosphorus-rich layer having been plasma planarized (smoothed by plasma etching). Moreover, the second level metallization can penetrate through apertures in both silicon dioxide layers to make contact with an underlying silicon semiconductor body in which the circuit is integrated.These apertures are preferably formed by anisotropic etching so as not to enlarge any cracks in the phosphorus-rich oxide layer, and a relatively thin layer of titanium nitride, for example, can optionally coat the sidewalls of the apertures to ensure further that aluminium of the second level metallization is not shorted through cracks in the phosphorus-rich oxide to the first level metallization.
In this way, the phosphorus-rich oxide layer ensures conformal contact with the first level metallization, as well as a satisfactorily ion-free quality of interface of this oxide layer with underlying field oxide; that is, the phosphorus-rich layer ensures satisfactory stability against ion migration which might otherwise cause spurious inversion layers or channels at the interface of the underlying silicon body with the field oxide. The phosphorus-poor oxide layer on the other hand prevents moisture absorption which would otherwise produce phosphoric acid, a corrosive agent which would deteriorate the conductivity of the underlying metallization. Such phosphoric acid formation would be especially deleterious in the presence of above-mentioned cracks in the phosphorus-rich oxide layer.
An embodiment of the invention will now be described by way of example with reference to the accompanying drawing which shows a sectional view of a portion of a semiconductor structure according to the invention.
For the sake of clarity the drawing is not to scale.
As shown in the drawing, a portion 100 of a semiconductor integrated circuit structure comprises a p-type single crystal silicon semiconductor body portion 10 having an n±type surface zone 101 at a horizontal major surface 105 of the body. A relatively thin, typically 250 A, thermally grown silicon dioxide layer 11 ("gate oxide") coats the major surface 105 overlying the zone 101 (except for the region of an aperture 21 in this gate oxide layer). A relatively thick, typically about 4,000 A, thermally grown layer of silicon dioxide 12 ("filed oxide") coats the remaining portion of the surface 105, that is, the portion complementary to that coated by the gate oxide.A first level metallization strip 13 of aluminium, typically about 7,000 A thick and about 2 micron wide as formed by selective masking and etching of a physically deposited aluminium layer (i.e. a layer deposited by evaporation or sputtering), overlies a portion of the field oxide layer 12. A plasma planarized, CVD deposited layer of phosphorus-rich silicon dioxide 14, typically about 10,000 A thick, overlies exposed surfaces of the gate oxide 11, the field oxide 12 and the first level metallization strip 13.
By "phosphorus-rich" silicon dioxide is meant an oxide layer containing at least about 6 percent by weight of phosphorus. Typically, however, the phosphorus content is kept below about 8 percent.
Illustratively, a pair of fissures 42 and 43 may undesirably propagate from corner edge surfaces of the first level strip 1 3 as shown. More specifically, the fissures 42 and 43 typically extend along directions of about 45 degrees with respect to the horizontal to a sidewall of the aperture 21 (at the level of the oxide layer 14) and to the top surface of the phosphorus-rich oxide layer 14.
The phosphorus-rich oxide layer 14 has an aperture 22 (down to the top surface of the first level strip 13) in addition to the aperture 21,to enable interconnection of the first level strip 13 with a second level metallization strip 162.
Upon the phosphorus-rich oxide layer 14 is located a phosphorus-poor oxide layer 15 having a thickness of typically about 5,000 A. By "phosphorus-poor" is meant a phosphorus content in the approximate range of O to 4 percent. Finally, the structure 100 includes second level metallization strips 161, 162, and 163, typically of aluminium having a thickness of about 12,000 A. These second level strips are typically formed (as was the first level strip 13) by a physical deposition process such as evaporation or sputtering and patterned by selective masking and dry reactive sputter etching. The aperture 21 extends through both oxide layers 1 5 and 14 as well as through the gate oxide layer 11 down to the n+ zone 101.
A useful sequence of steps to fabricate the structure 100 includes first forming the thick field oxide layer 12 over a limited portion of the surface 105, thermally growing the thin gate oxide layer 11, and then forming the zone 101 by introduction of impurities, such as by ion implantation using the thick field oxide as a protective mask against introduction of the impurities.
Then the first level metallization strip 13 is formed by a physical deposition process followed by masking and etching. (This first level strip is formed before the aperture 21 in the gate oxide 11). It is preferred that this first level metallization does not comprise polycrystalline silicon or any other material that is susceptible to being etched by the same process used for etching either the gate oxide 11, the phosphorus-rich oxide layer 14, or the phosphorus-poor oxide layer 15~lest the first level metallization be undesirably etched during the etching of apertures 21 and 22.
Then a phosphorus-rich oxide layer is deposited by a CVD step involving typically the chemcial reaction of SiH4 and PH3 with oxygen at a pressure of about 1.0 torr and temperature of about 4400 C, and subsequently this deposited oxide layer is plasma planarized to form the phosphorus-rich oxide layer 14 with a planar top surface. Fissures 42 and 43 may develope in the layer 1 4 during deposition, because of the sharp corner edges of the first level metallization at its interface with the field oxide 12. These fissures remain after plasma planarization.The planarization of this oxide layer 14 can be achieved by first depositing a phosphorus-rich oxide layer with a thickness well in excess of the ultimately desired value, and then depositing a thick, smooth-topped sacrificial layer (typically of polymer or spun-on resist) thereon having an etch rate substantially equal to that of the phosphorusrich oxide and of sufficient thickness to have a top surface which is substantially planar, and then plasma etching with a mixture of CF4 and about 8 percent by volume of oxygen, for example, at about 50 to 600C in order to remove entirely the sacrificial layer-all as described more fully by A.
C. Adams in "Plasma Planarization", Solid State Technology, Viol.24, pp.178-181 (April 1981).
Next the phosphorus-poor oxide layer 15 is deposited, typically by a low pressure (at or below about 1.0 mm Hg) CVD step involving the chemical reaction of SiH4 with oxygen at a temperature of about 4400 C. Then the apertures 21 and 22 are opened, through the oxide layers 1 5, 14, and 11 for the aperture 21 and through the oxide layers 15 and 14 for the aperture 22.
For opening these apertures, an anisotropic etching process should be used, in order not to enlarge the fissure 42. That is, a physical process-such as reactive ion etching with CHF3-should be used. Steep sidewalls of the apertures 21 and 22 thus result.
A thin layer of sealent, such as titanium nitride may then be applied to seal such fissures as fissure 42. This sealant is believed not to be essential in many applications because of the formation, during the etching of the aperture 21, of an insluating polymer-for example, of silicon carbide-fluoride-oxide-which seals the fissure 42. Moreover, in many integrated circuits there are statistically significantly fewer opportunities for fissures to be present (of the kind formed by the fissure 42) running to the sidewalls of apertures than for fissures (like fissure 43) to be present running to the interface of the oxide layers 14 and 15, and hence there is a smaller failure probability occasioned by fissures such as fissure 42 than by fissures such as fissure 43.
Finally, a second level metallization of aluminium is formed in a pattern of second level metallization strips 161,162,163 on the top of the structure 100 by conventional techniques of physical deposition followed by selective masking and etching.
It will be appreciated how the strip 1 61, for example, is isolated from the fissure 43, and hence insulated from the first level strip 13, by the phosphorus-poor oxide layer 15. This oxide layer 15, it should be noted, is deposited over a planarized surface of the phosphorus-rich oxide layer 14, and therefore presents a desirably smooth (planar) surface for deposition thereon-of the second level metallization.
Although the invention has been described in terms of a specific embodiment, various modifications can be made without departing from the scope of the invention. For example, instead of using CHF3 for etching the apertures 21 and 22, other anisotropic reactive ion etchants of silicon dioxide can be used, such as a mixture of CHF3 and NH3, or of CHEF, and 02, or of CHF3 and CO2. Instead of titanium nitride for sealing the fissure 42, other sealants can be used, such as molybdenum.

Claims (6)

Claims
1. A semiconductor integrated circuit structure including a semiconductor body and first level metallization and second level metallization with mutual insulation therebetween comprising a phosphorus-rich silicon dioxide layer and a phosphorus-poor silicon dioxide layer located on the phosphorus-rich layer.
2. A structure as claimed in claim 1 wherein the semiconductor body is of single crystal silicon and the first and second level metallizations are both of aluminium.
3. A structure as claimed in claim 1 or claim 2 wherein the first level metallization is separated from the semiconductor body by a field oxide layer, the phosphorus-rich layer is a planarized layer and the phosphorus-poor layer is a chemical vapour deposited layer.
4. A structure as claimed in any of the preceding claims wherein a strip of the second level metallization contacts a strip of the first level metallization through an anisotropically etched aperture penetrating both the phosphorus-poor and the phosphorus-rich layers.
5. A structure as claimed in any of the preceding claims wherein the phosphorus-rich oxide layer contains at least 6 percent phosphorus and the phosphorus-poor oxide layer contains less than 4 percent phosphorus.
6. A semiconductor integrated circuit substantially as herein described with reference to the accompanying drawing.
GB08310669A 1982-04-23 1983-04-20 Insulation layer between metallization in a semiconductor integrated circuit structure Withdrawn GB2118777A (en)

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US37105582A 1982-04-23 1982-04-23

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GB2118777A true GB2118777A (en) 1983-11-02

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EP (1) EP0105915A1 (en)
ES (1) ES8403666A1 (en)
GB (1) GB2118777A (en)
IT (1) IT1170132B (en)
WO (1) WO1983003923A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0206937A2 (en) * 1985-06-21 1986-12-30 Fairchild Semiconductor Corporation Stress relieved intermediate insulating layer for multilayer metalization
US4725566A (en) * 1985-06-11 1988-02-16 Thomson-Csf Method of forming at least two metallizations of a semiconductor component, covered with a dielectric layer
US5424570A (en) * 1992-01-31 1995-06-13 Sgs-Thomson Microelectronics, Inc. Contact structure for improving photoresist adhesion on a dielectric layer

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60198847A (en) * 1984-03-23 1985-10-08 Nec Corp Semiconductor device and manufacture thereof
JPH088265B2 (en) * 1988-09-13 1996-01-29 株式会社東芝 Compound semiconductor device and manufacturing method thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2092376A (en) * 1980-12-29 1982-08-11 Nippon Electric Co Improvements in semiconductor devices

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US3882530A (en) * 1971-12-09 1975-05-06 Us Government Radiation hardening of mos devices by boron
US4005455A (en) * 1974-08-21 1977-01-25 Intel Corporation Corrosive resistant semiconductor interconnect pad
JPS5171068A (en) * 1974-12-16 1976-06-19 Matsushita Electronics Corp HANDOTA ISOCHI
JPS54147789A (en) * 1978-05-11 1979-11-19 Matsushita Electric Ind Co Ltd Semiconductor divice and its manufacture
JPS577153A (en) * 1980-06-16 1982-01-14 Nec Corp Preparation of semiconductor device
JPS6046546B2 (en) * 1980-06-16 1985-10-16 日本電気株式会社 Manufacturing method of semiconductor device
JPS5727047A (en) * 1980-07-25 1982-02-13 Seiko Epson Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2092376A (en) * 1980-12-29 1982-08-11 Nippon Electric Co Improvements in semiconductor devices

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4725566A (en) * 1985-06-11 1988-02-16 Thomson-Csf Method of forming at least two metallizations of a semiconductor component, covered with a dielectric layer
EP0206937A2 (en) * 1985-06-21 1986-12-30 Fairchild Semiconductor Corporation Stress relieved intermediate insulating layer for multilayer metalization
EP0206937A3 (en) * 1985-06-21 1987-09-02 Fairchild Semiconductor Corporation Stress relieved intermediate insulating layer for multilayer metalization
US5424570A (en) * 1992-01-31 1995-06-13 Sgs-Thomson Microelectronics, Inc. Contact structure for improving photoresist adhesion on a dielectric layer
US5877541A (en) * 1992-01-31 1999-03-02 Stmicroelectronics, Inc. Contact structure for improving photoresist adhesion on a dielectric layer

Also Published As

Publication number Publication date
GB8310669D0 (en) 1983-05-25
WO1983003923A1 (en) 1983-11-10
EP0105915A1 (en) 1984-04-25
ES521708A0 (en) 1984-04-01
IT1170132B (en) 1987-06-03
IT8320700A0 (en) 1983-04-20
ES8403666A1 (en) 1984-04-01

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