JPS6211491B2 - - Google Patents

Info

Publication number
JPS6211491B2
JPS6211491B2 JP56188654A JP18865481A JPS6211491B2 JP S6211491 B2 JPS6211491 B2 JP S6211491B2 JP 56188654 A JP56188654 A JP 56188654A JP 18865481 A JP18865481 A JP 18865481A JP S6211491 B2 JPS6211491 B2 JP S6211491B2
Authority
JP
Japan
Prior art keywords
semiconductor wafer
mask
alignment mark
layer
mask layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56188654A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5890728A (ja
Inventor
Hiroo Kinoshita
Toshiro Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56188654A priority Critical patent/JPS5890728A/ja
Publication of JPS5890728A publication Critical patent/JPS5890728A/ja
Publication of JPS6211491B2 publication Critical patent/JPS6211491B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
JP56188654A 1981-11-25 1981-11-25 半導体ウエファ上の位置合せ用マ−クの製法 Granted JPS5890728A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56188654A JPS5890728A (ja) 1981-11-25 1981-11-25 半導体ウエファ上の位置合せ用マ−クの製法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56188654A JPS5890728A (ja) 1981-11-25 1981-11-25 半導体ウエファ上の位置合せ用マ−クの製法

Publications (2)

Publication Number Publication Date
JPS5890728A JPS5890728A (ja) 1983-05-30
JPS6211491B2 true JPS6211491B2 (fr) 1987-03-12

Family

ID=16227497

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56188654A Granted JPS5890728A (ja) 1981-11-25 1981-11-25 半導体ウエファ上の位置合せ用マ−クの製法

Country Status (1)

Country Link
JP (1) JPS5890728A (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6218714A (ja) * 1985-07-18 1987-01-27 Nippon Telegr & Teleph Corp <Ntt> アライメントマ−クの形成方法
JP2855868B2 (ja) * 1990-03-12 1999-02-10 富士通株式会社 レーザトリミング用位置合わせマーク、半導体装置及び半導体装置の製造方法
KR950002171B1 (ko) * 1990-03-12 1995-03-14 후지쓰 가부시끼가이샤 얼라인먼트마크및반도체장치
US6914017B1 (en) 2000-08-30 2005-07-05 Micron Technology, Inc. Residue free overlay target
JP5425363B2 (ja) * 2006-11-28 2014-02-26 ルネサスエレクトロニクス株式会社 半導体装置、及び表示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49113581A (fr) * 1973-02-26 1974-10-30
JPS5253668A (en) * 1975-10-29 1977-04-30 Hitachi Ltd Production of semiconductor device
JPS5494881A (en) * 1978-01-12 1979-07-26 Nippon Telegr & Teleph Corp <Ntt> Exposure method
JPS5674936A (en) * 1979-11-22 1981-06-20 Sharp Corp Position detection method of semiconductor chip

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49113581A (fr) * 1973-02-26 1974-10-30
JPS5253668A (en) * 1975-10-29 1977-04-30 Hitachi Ltd Production of semiconductor device
JPS5494881A (en) * 1978-01-12 1979-07-26 Nippon Telegr & Teleph Corp <Ntt> Exposure method
JPS5674936A (en) * 1979-11-22 1981-06-20 Sharp Corp Position detection method of semiconductor chip

Also Published As

Publication number Publication date
JPS5890728A (ja) 1983-05-30

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