JPS5890728A - 半導体ウエファ上の位置合せ用マ−クの製法 - Google Patents
半導体ウエファ上の位置合せ用マ−クの製法Info
- Publication number
- JPS5890728A JPS5890728A JP56188654A JP18865481A JPS5890728A JP S5890728 A JPS5890728 A JP S5890728A JP 56188654 A JP56188654 A JP 56188654A JP 18865481 A JP18865481 A JP 18865481A JP S5890728 A JPS5890728 A JP S5890728A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- alignment mark
- regions
- mask
- mask layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000005530 etching Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 14
- 238000001020 plasma etching Methods 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 22
- 239000000463 material Substances 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 210000000554 iris Anatomy 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56188654A JPS5890728A (ja) | 1981-11-25 | 1981-11-25 | 半導体ウエファ上の位置合せ用マ−クの製法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56188654A JPS5890728A (ja) | 1981-11-25 | 1981-11-25 | 半導体ウエファ上の位置合せ用マ−クの製法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5890728A true JPS5890728A (ja) | 1983-05-30 |
JPS6211491B2 JPS6211491B2 (fr) | 1987-03-12 |
Family
ID=16227497
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56188654A Granted JPS5890728A (ja) | 1981-11-25 | 1981-11-25 | 半導体ウエファ上の位置合せ用マ−クの製法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5890728A (fr) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6218714A (ja) * | 1985-07-18 | 1987-01-27 | Nippon Telegr & Teleph Corp <Ntt> | アライメントマ−クの形成方法 |
JPH04330710A (ja) * | 1990-03-12 | 1992-11-18 | Fujitsu Ltd | レーザトリミング用位置合わせマーク、半導体装置、及び半導体装置の製造方法 |
US5528372A (en) * | 1990-03-12 | 1996-06-18 | Fujitsu Limited | Alignment mark, laser trimmer and semiconductor device manufacturing process |
US6822342B2 (en) | 2000-08-30 | 2004-11-23 | Micron Technology, Inc. | Raised-lines overlay semiconductor targets and method of making the same |
JP2008135495A (ja) * | 2006-11-28 | 2008-06-12 | Nec Electronics Corp | 半導体装置、及び表示装置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49113581A (fr) * | 1973-02-26 | 1974-10-30 | ||
JPS5253668A (en) * | 1975-10-29 | 1977-04-30 | Hitachi Ltd | Production of semiconductor device |
JPS5494881A (en) * | 1978-01-12 | 1979-07-26 | Nippon Telegr & Teleph Corp <Ntt> | Exposure method |
JPS5674936A (en) * | 1979-11-22 | 1981-06-20 | Sharp Corp | Position detection method of semiconductor chip |
-
1981
- 1981-11-25 JP JP56188654A patent/JPS5890728A/ja active Granted
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49113581A (fr) * | 1973-02-26 | 1974-10-30 | ||
JPS5253668A (en) * | 1975-10-29 | 1977-04-30 | Hitachi Ltd | Production of semiconductor device |
JPS5494881A (en) * | 1978-01-12 | 1979-07-26 | Nippon Telegr & Teleph Corp <Ntt> | Exposure method |
JPS5674936A (en) * | 1979-11-22 | 1981-06-20 | Sharp Corp | Position detection method of semiconductor chip |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6218714A (ja) * | 1985-07-18 | 1987-01-27 | Nippon Telegr & Teleph Corp <Ntt> | アライメントマ−クの形成方法 |
JPH04330710A (ja) * | 1990-03-12 | 1992-11-18 | Fujitsu Ltd | レーザトリミング用位置合わせマーク、半導体装置、及び半導体装置の製造方法 |
US5528372A (en) * | 1990-03-12 | 1996-06-18 | Fujitsu Limited | Alignment mark, laser trimmer and semiconductor device manufacturing process |
US6822342B2 (en) | 2000-08-30 | 2004-11-23 | Micron Technology, Inc. | Raised-lines overlay semiconductor targets and method of making the same |
US6914017B1 (en) * | 2000-08-30 | 2005-07-05 | Micron Technology, Inc. | Residue free overlay target |
JP2008135495A (ja) * | 2006-11-28 | 2008-06-12 | Nec Electronics Corp | 半導体装置、及び表示装置 |
Also Published As
Publication number | Publication date |
---|---|
JPS6211491B2 (fr) | 1987-03-12 |
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