JPS6112307B2 - - Google Patents

Info

Publication number
JPS6112307B2
JPS6112307B2 JP953183A JP953183A JPS6112307B2 JP S6112307 B2 JPS6112307 B2 JP S6112307B2 JP 953183 A JP953183 A JP 953183A JP 953183 A JP953183 A JP 953183A JP S6112307 B2 JPS6112307 B2 JP S6112307B2
Authority
JP
Japan
Prior art keywords
status information
data
buffer
queue
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP953183A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59135528A (ja
Inventor
Nobuaki Kitamura
Hiroaki Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP953183A priority Critical patent/JPS59135528A/ja
Publication of JPS59135528A publication Critical patent/JPS59135528A/ja
Publication of JPS6112307B2 publication Critical patent/JPS6112307B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
JP953183A 1983-01-24 1983-01-24 多重待行列バツフア回路 Granted JPS59135528A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP953183A JPS59135528A (ja) 1983-01-24 1983-01-24 多重待行列バツフア回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP953183A JPS59135528A (ja) 1983-01-24 1983-01-24 多重待行列バツフア回路

Publications (2)

Publication Number Publication Date
JPS59135528A JPS59135528A (ja) 1984-08-03
JPS6112307B2 true JPS6112307B2 (cg-RX-API-DMAC7.html) 1986-04-07

Family

ID=11722845

Family Applications (1)

Application Number Title Priority Date Filing Date
JP953183A Granted JPS59135528A (ja) 1983-01-24 1983-01-24 多重待行列バツフア回路

Country Status (1)

Country Link
JP (1) JPS59135528A (cg-RX-API-DMAC7.html)

Also Published As

Publication number Publication date
JPS59135528A (ja) 1984-08-03

Similar Documents

Publication Publication Date Title
JP2916045B2 (ja) Fifoモジュール
US4809161A (en) Data storage device
EP0839354B1 (en) Memory structure
EP0367995B1 (en) Vector data transfer controller
JPS6112307B2 (cg-RX-API-DMAC7.html)
JPH10112178A (ja) Fifoメモリおよびその製造方法
JP2595992B2 (ja) 電子楽器
JPS6054056A (ja) ビットデ−タ書込メモリインタ−フェ−ス回路
EP0353942A2 (en) A ripple-through FIFO memory
JPS6155686B2 (cg-RX-API-DMAC7.html)
JP4464245B2 (ja) データキュー制御回路、方法及びプログラム
JP2748404B2 (ja) 2項データメモリ
JP2917290B2 (ja) レジスタ制御回路
JPH113209A (ja) 動的な資源利用機能を備えたデータ処理システム
JPS6327731B2 (cg-RX-API-DMAC7.html)
JPH10241354A (ja) 双方向転送型記憶装置及びメモリの入出力制御方法
JPS581817B2 (ja) 待行列制御方式
JPH0652677A (ja) Fifoメモリ
JPH0559448B2 (cg-RX-API-DMAC7.html)
JPH044631B2 (cg-RX-API-DMAC7.html)
JPH03201733A (ja) データワードの時間組込み処理方法及びその方法を実施する装置
JPS61182136A (ja) デ−タ流待ち合せ回路
JPS583171A (ja) メモリ方式
JPH06250915A (ja) 拡張記憶制御方式
JPH03189998A (ja) シフトレジスタ回路