JPS59135528A - 多重待行列バツフア回路 - Google Patents

多重待行列バツフア回路

Info

Publication number
JPS59135528A
JPS59135528A JP953183A JP953183A JPS59135528A JP S59135528 A JPS59135528 A JP S59135528A JP 953183 A JP953183 A JP 953183A JP 953183 A JP953183 A JP 953183A JP S59135528 A JPS59135528 A JP S59135528A
Authority
JP
Japan
Prior art keywords
status information
data
queue
buffer
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP953183A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6112307B2 (cg-RX-API-DMAC7.html
Inventor
Nobuaki Kitamura
北村　暢明
Hiroaki Sato
博昭 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP953183A priority Critical patent/JPS59135528A/ja
Publication of JPS59135528A publication Critical patent/JPS59135528A/ja
Publication of JPS6112307B2 publication Critical patent/JPS6112307B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
JP953183A 1983-01-24 1983-01-24 多重待行列バツフア回路 Granted JPS59135528A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP953183A JPS59135528A (ja) 1983-01-24 1983-01-24 多重待行列バツフア回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP953183A JPS59135528A (ja) 1983-01-24 1983-01-24 多重待行列バツフア回路

Publications (2)

Publication Number Publication Date
JPS59135528A true JPS59135528A (ja) 1984-08-03
JPS6112307B2 JPS6112307B2 (cg-RX-API-DMAC7.html) 1986-04-07

Family

ID=11722845

Family Applications (1)

Application Number Title Priority Date Filing Date
JP953183A Granted JPS59135528A (ja) 1983-01-24 1983-01-24 多重待行列バツフア回路

Country Status (1)

Country Link
JP (1) JPS59135528A (cg-RX-API-DMAC7.html)

Also Published As

Publication number Publication date
JPS6112307B2 (cg-RX-API-DMAC7.html) 1986-04-07

Similar Documents

Publication Publication Date Title
US3731284A (en) Method and apparatus for reordering data
EP0839354B1 (en) Memory structure
US6208275B1 (en) Method and apparatus for digital concatenation
JPS63183679A (ja) 高速ポインタをベースとした先入先出メモリ
US4761732A (en) Interrupt controller arrangement for mutually exclusive interrupt signals in data processing systems
US4521874A (en) Random access memory device
EP0416513A2 (en) Fifo memory device
EP0367995A2 (en) Vector data transfer controller
JPS59135528A (ja) 多重待行列バツフア回路
US20060004980A1 (en) Address creator and arithmetic circuit
USRE36026E (en) Programmable device for storing digital video lines
JPH10112178A (ja) Ｆｉｆｏメモリおよびその製造方法
JPWO2008099472A1 (ja) データスイッチ方法及び回路
US4538260A (en) Electronic time switch
HK44396A (en) Data processing system with cyclic data buffering, selecting means for selecting memory addresses, suitable for use in such a system
JPS6155686B2 (cg-RX-API-DMAC7.html)
JP2009055257A (ja) データ間引き処理方法およびデータ間引き処理回路
EP0353942A2 (en) A ripple-through FIFO memory
US4933894A (en) Circuit and method for adding binary numbers with a difference of one or less
JPH03201733A (ja) データワードの時間組込み処理方法及びその方法を実施する装置
JPH113209A (ja) 動的な資源利用機能を備えたデータ処理システム
JP2532092B2 (ja) 状態保持回路走査方式
JPH03171273A (ja) デジタル信号処理装置
JPH0638319B2 (ja) 可変段数シフトレジスタ
JPS6327731B2 (cg-RX-API-DMAC7.html)