JPS6098652A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6098652A
JPS6098652A JP20696883A JP20696883A JPS6098652A JP S6098652 A JPS6098652 A JP S6098652A JP 20696883 A JP20696883 A JP 20696883A JP 20696883 A JP20696883 A JP 20696883A JP S6098652 A JPS6098652 A JP S6098652A
Authority
JP
Japan
Prior art keywords
semiconductor chip
bonding
pads
package
same signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20696883A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0216013B2 (enrdf_load_stackoverflow
Inventor
Toshiyuki Ogawa
小川　俊行
Yoichi Hida
洋一 飛田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP20696883A priority Critical patent/JPS6098652A/ja
Publication of JPS6098652A publication Critical patent/JPS6098652A/ja
Publication of JPH0216013B2 publication Critical patent/JPH0216013B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
JP20696883A 1983-11-02 1983-11-02 半導体装置 Granted JPS6098652A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20696883A JPS6098652A (ja) 1983-11-02 1983-11-02 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20696883A JPS6098652A (ja) 1983-11-02 1983-11-02 半導体装置

Publications (2)

Publication Number Publication Date
JPS6098652A true JPS6098652A (ja) 1985-06-01
JPH0216013B2 JPH0216013B2 (enrdf_load_stackoverflow) 1990-04-13

Family

ID=16531982

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20696883A Granted JPS6098652A (ja) 1983-11-02 1983-11-02 半導体装置

Country Status (1)

Country Link
JP (1) JPS6098652A (enrdf_load_stackoverflow)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62114256A (ja) * 1985-11-13 1987-05-26 Mitsubishi Electric Corp 半導体装置
JPS63208235A (ja) * 1987-02-24 1988-08-29 Nec Corp 半導体装置
JPH01107548A (ja) * 1987-10-20 1989-04-25 Hitachi Ltd 半導体装置
US4974053A (en) * 1988-10-06 1990-11-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device for multiple packaging configurations
US4990996A (en) * 1987-12-18 1991-02-05 Zilog, Inc. Bonding pad scheme
JPH03238839A (ja) * 1990-02-15 1991-10-24 Nec Corp 半導体集積回路装置
US5905300A (en) * 1994-03-31 1999-05-18 Vlsi Technology, Inc. Reinforced leadframe to substrate attachment
US5965948A (en) * 1995-02-28 1999-10-12 Nec Corporation Semiconductor device having doubled pads

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0635910U (ja) * 1992-10-16 1994-05-13 株式会社ニコン ビーム射出装置
JPH0657572U (ja) * 1993-01-14 1994-08-09 レーザーテクノ株式会社 墨出し用レーザー装置
JP7079889B1 (ja) 2021-11-30 2022-06-02 株式会社タムラ製作所 はんだ合金、はんだ接合材、ソルダペースト及び半導体パッケージ

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5173973U (enrdf_load_stackoverflow) * 1974-12-05 1976-06-10
JPS5456360A (en) * 1977-10-14 1979-05-07 Hitachi Ltd Production of semiconductor chips
JPS5895044U (ja) * 1981-12-18 1983-06-28 セイコーインスツルメンツ株式会社 Ｉｃチツプの端子構造

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5173973U (enrdf_load_stackoverflow) * 1974-12-05 1976-06-10
JPS5456360A (en) * 1977-10-14 1979-05-07 Hitachi Ltd Production of semiconductor chips
JPS5895044U (ja) * 1981-12-18 1983-06-28 セイコーインスツルメンツ株式会社 Ｉｃチツプの端子構造

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62114256A (ja) * 1985-11-13 1987-05-26 Mitsubishi Electric Corp 半導体装置
JPS63208235A (ja) * 1987-02-24 1988-08-29 Nec Corp 半導体装置
JPH01107548A (ja) * 1987-10-20 1989-04-25 Hitachi Ltd 半導体装置
US4990996A (en) * 1987-12-18 1991-02-05 Zilog, Inc. Bonding pad scheme
US4974053A (en) * 1988-10-06 1990-11-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device for multiple packaging configurations
JPH03238839A (ja) * 1990-02-15 1991-10-24 Nec Corp 半導体集積回路装置
US5905300A (en) * 1994-03-31 1999-05-18 Vlsi Technology, Inc. Reinforced leadframe to substrate attachment
US5965948A (en) * 1995-02-28 1999-10-12 Nec Corporation Semiconductor device having doubled pads

Also Published As

Publication number Publication date
JPH0216013B2 (enrdf_load_stackoverflow) 1990-04-13

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