JPH02105450A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH02105450A
JPH02105450A JP63258680A JP25868088A JPH02105450A JP H02105450 A JPH02105450 A JP H02105450A JP 63258680 A JP63258680 A JP 63258680A JP 25868088 A JP25868088 A JP 25868088A JP H02105450 A JPH02105450 A JP H02105450A
Authority
JP
Japan
Prior art keywords
semiconductor chip
bonded
die
island
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63258680A
Other languages
English (en)
Inventor
Hideto Nitta
新田　秀人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63258680A priority Critical patent/JPH02105450A/ja
Publication of JPH02105450A publication Critical patent/JPH02105450A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の構造に関する。
〔従来の技術〕
従来、半導体装置に、例えば、リードフレーム上のアイ
ランドに半導体チップをダイボンディングし、半導体チ
ップ内の所定のパッドと、リードフレーム上の所定部と
をワイヤボンディングにて接続し、トランスファモール
ド法にて樹脂封止したものがある。
〔発明が解決しようとする課題〕
上述した従来の半導体装置は、アイランドの上部には半
導体チップを搭載しているが、アイランドの下部の領域
は、樹脂により充填されているだけで、半導体装置の全
体の体積に占める半導体チップの体積比を小さくする一
因となっている。すなわち、従来の半導体装置は、アイ
ランドの下部領域を有効に利用していないという欠点が
ある。
〔課題を解決するための手段〕
本発明の半導体装置は、アイランド上に半導体チップを
ダイボンディングし、半導体チップ内のパッドと外部リ
ード上の所定部とをワイヤボンディングしたリードフレ
ーム２個を、それぞれのリードフレームの裏面を互いに
合わせ樹脂封止した構造を有することを特徴とする。
〔実施例〕
次に本発明について図面を参照して説明する。
第１図は本発明の第１の実施例の縦断面図である。アイ
ランドｌａ上に半導体チップ２ａをダイボンディングし
、さらに、半導体チップ２ａ内のバッドと外部リード３
ａの所定部とを例えば金線５ａにてワイヤボンディング
したリードフレーム４ａと、アイランドｌｂ上に半導体
チップ２ｂをダイボンディングし、半導体チップ２ｂ内
のバットと外部リード３ｂの所定部とを金線５ｂにてワ
イヤボディングしたリードフレーム４ｂとを半導体チッ
プ２ａ、２ｂかダイボンディングされていない面（裏面
）を合わせてトランスファモールド法にて樹脂封止し、
外部リードを所定の形状に切断・成形することにより、
本発明による半導体装置が得られる。
第２図は、本発明の第２の実施例の斜視図である。外部
リード３ａ、３ｂをリードフレームを、裏面を合わせた
時に、互いに重ならない用にちどりに配置した例である
。
〔発明の効果〕
以上、説明したように本発明は、２枚のリードフレーム
の裏面を互いに合わせてトランスファモールド法などに
より樹脂封止することにより、従来と同一の外形を有す
るパッケージ内に半導体チップを複数個搭載可能となり
、半導体装置全体の体積における半導体チップの占める
体積比を大きくできる効果がある。
【図面の簡単な説明】
第１図は本発明の第１の実施例の縦断面図、第２図は、
本発明の第２め実施例の斜視図である。 ｌａ、ｌｂ・・・アイランド、２ａ、２ｂ・・・半導体
チップ、３ａ、３ｂ・・・外部リード、４ａ、４ｂ・・
・リードフレーム、５ａ、５ｂ・・・金線。

Claims (1)

    【特許請求の範囲】
  1. アイランド上に半導体チップをダイボンディングし、該
    半導体チップ内のパッドと外部リード上の所定部とをワ
    イヤボンディングしたリードフレーム２個を、リードフ
    レームの裏面を互いに合せて樹脂封止したことを特徴と
    する半導体装置。
JP63258680A 1988-10-13 1988-10-13 半導体装置 Pending JPH02105450A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63258680A JPH02105450A (ja) 1988-10-13 1988-10-13 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63258680A JPH02105450A (ja) 1988-10-13 1988-10-13 半導体装置

Publications (1)

Publication Number Publication Date
JPH02105450A true JPH02105450A (ja) 1990-04-18

Family

ID=17323609

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63258680A Pending JPH02105450A (ja) 1988-10-13 1988-10-13 半導体装置

Country Status (1)

Country Link
JP (1) JPH02105450A (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5543658A (en) * 1993-06-14 1996-08-06 Kabushiki Kaisha Toshiba Method of manufacturing resin-sealed semiconductor device, lead frame used in this method for mounting plurality of semiconductor elements, and resin-sealed semiconductor device
US5585668A (en) * 1995-01-30 1996-12-17 Staktek Corporation Integrated circuit package with overlapped die on a common lead frame
US5646829A (en) * 1994-11-25 1997-07-08 Sharp Kabushiki Kaisha Resin sealing type semiconductor device having fixed inner leads
JP2009064854A (ja) * 2007-09-05 2009-03-26 Nec Electronics Corp リードフレーム、半導体装置、及び半導体装置の製造方法
JP2011243626A (ja) * 2010-05-14 2011-12-01 Mitsubishi Electric Corp 半導体モジュールとその製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54144872A (en) * 1978-05-04 1979-11-12 Omron Tateisi Electronics Co Electronic circuit device
JPS6127248B2 (ja) * 1980-01-30 1986-06-24 Toyo Ekoo Kk
JPS6273748A (ja) * 1985-09-27 1987-04-04 Toshiba Corp 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54144872A (en) * 1978-05-04 1979-11-12 Omron Tateisi Electronics Co Electronic circuit device
JPS6127248B2 (ja) * 1980-01-30 1986-06-24 Toyo Ekoo Kk
JPS6273748A (ja) * 1985-09-27 1987-04-04 Toshiba Corp 半導体装置

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5543658A (en) * 1993-06-14 1996-08-06 Kabushiki Kaisha Toshiba Method of manufacturing resin-sealed semiconductor device, lead frame used in this method for mounting plurality of semiconductor elements, and resin-sealed semiconductor device
US5614441A (en) * 1993-06-14 1997-03-25 Kabushiki Kaisha Toshiba Process of folding a strip leadframe to superpose two leadframes in a plural semiconductor die encapsulated package
US5646829A (en) * 1994-11-25 1997-07-08 Sharp Kabushiki Kaisha Resin sealing type semiconductor device having fixed inner leads
US5585668A (en) * 1995-01-30 1996-12-17 Staktek Corporation Integrated circuit package with overlapped die on a common lead frame
JP2009064854A (ja) * 2007-09-05 2009-03-26 Nec Electronics Corp リードフレーム、半導体装置、及び半導体装置の製造方法
JP2011243626A (ja) * 2010-05-14 2011-12-01 Mitsubishi Electric Corp 半導体モジュールとその製造方法

Similar Documents

Publication Publication Date Title
WO1998052217A3 (en) Method of forming a chip scale package, and a tool used in forming the chip scale package
JP2003115573A (ja) デュアルダイパッケージ
JPH04302164A (ja) 半導体装置
JPH02105450A (ja) 半導体装置
JP2716405B2 (ja) 半導体装置およびその製造方法
JPH07101698B2 (ja) 樹脂封止型半導体装置の製造方法
JP2845841B2 (ja) 半導体装置
JPH0461152A (ja) 半導体装置
US20080038872A1 (en) Method of manufacturing semiconductor device
JPH03105950A (ja) 半導体集積回路のパッケージ
JPH0621305A (ja) 半導体装置
JP3847432B2 (ja) 樹脂封止半導体装置及びその製造方法
JPH08279575A (ja) 半導体パッケージ
KR100267220B1 (ko) 반도체소자패키지및그의제조방법
KR100218291B1 (ko) 세라믹 패들을 이용한 반도체 패키지 및 그 제작방법
KR0124545Y1 (ko) 스텝형 패키지
KR100239684B1 (ko) 멀티칩패키지(mcp) 제작방법 및 그 구조
KR950014116B1 (ko) 반도체 장치 및 그 제조방법
KR100370480B1 (ko) 반도체 패키지용 리드 프레임
KR100345163B1 (ko) 볼 그리드 어레이 패키지
JPH06132475A (ja) 半導体パッケージ
JPH0422159A (ja) 半導体集積回路装置およびその製造方法
JPH04348538A (ja) ワイヤーボンディング構造
KR200154510Y1 (ko) 리드 온 칩 패키지
JPH0555452A (ja) 半導体集積回路装置