JPS6035249Y2 - 半導体装置用回路基板 - Google Patents
半導体装置用回路基板Info
- Publication number
- JPS6035249Y2 JPS6035249Y2 JP1980170660U JP17066080U JPS6035249Y2 JP S6035249 Y2 JPS6035249 Y2 JP S6035249Y2 JP 1980170660 U JP1980170660 U JP 1980170660U JP 17066080 U JP17066080 U JP 17066080U JP S6035249 Y2 JPS6035249 Y2 JP S6035249Y2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- pattern
- circuit board
- alignment pattern
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Landscapes
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1980170660U JPS6035249Y2 (ja) | 1980-11-27 | 1980-11-27 | 半導体装置用回路基板 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1980170660U JPS6035249Y2 (ja) | 1980-11-27 | 1980-11-27 | 半導体装置用回路基板 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5793148U JPS5793148U (enrdf_load_stackoverflow) | 1982-06-08 |
| JPS6035249Y2 true JPS6035249Y2 (ja) | 1985-10-19 |
Family
ID=29529087
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1980170660U Expired JPS6035249Y2 (ja) | 1980-11-27 | 1980-11-27 | 半導体装置用回路基板 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6035249Y2 (enrdf_load_stackoverflow) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5339235B2 (enrdf_load_stackoverflow) * | 1974-02-06 | 1978-10-20 | ||
| JPS5237768A (en) * | 1975-09-19 | 1977-03-23 | Seiko Instr & Electronics Ltd | Substrate having positioning marks |
| JPS5847704Y2 (ja) * | 1978-04-10 | 1983-10-31 | 日本電気株式会社 | 半導体装置用容器 |
-
1980
- 1980-11-27 JP JP1980170660U patent/JPS6035249Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5793148U (enrdf_load_stackoverflow) | 1982-06-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW490716B (en) | Apparatus, method and product therefrom, for aligning die to interconnect metal on flex substrate | |
| KR100596522B1 (ko) | 전자회로 장치의 제조방법 및 전자회로 장치 | |
| JP3263871B2 (ja) | 基板および基板の位置合わせ方法 | |
| US6975040B2 (en) | Fabricating semiconductor chips | |
| JPS6035249Y2 (ja) | 半導体装置用回路基板 | |
| KR20050003803A (ko) | 반도체 패키지의 서브스트레이트 | |
| CN115360108B (zh) | 一种高精度对准方法 | |
| JP2739269B2 (ja) | 表示装置の製造方法 | |
| JPH01119088A (ja) | 表面実装部品搭載用プリント配線板 | |
| JPH05335438A (ja) | リードレスチップキャリア | |
| JP2661540B2 (ja) | 半導体チップ、ｔａｂテープ及びインナーリードボンダー並びに半導体装置の製造方法 | |
| JP2833174B2 (ja) | 半導体素子及びその実装方法 | |
| JPH03101142A (ja) | 半導体装置の製造方法 | |
| JP3284048B2 (ja) | 半導体装置およびその製造方法 | |
| JPH0666240B2 (ja) | 半導体装置の製造方法 | |
| JPH07240431A (ja) | 回路基板の位置合わせマークとその製造方法 | |
| JP3070145B2 (ja) | 半導体装置 | |
| JP3301112B2 (ja) | マルチチップパッケージ型半導体装置の製造方法 | |
| JP2534515B2 (ja) | 電子部品搭載用基板 | |
| JPH09223722A (ja) | 位置認識マーク及びｔａｂテープ及び半導体装置及びプリント基板 | |
| JPS6359595A (ja) | 携帯可能媒体における実装方法 | |
| JPH065729A (ja) | プリント配線板および半導体素子の位置合わせ方法 | |
| JPH0347550B2 (enrdf_load_stackoverflow) | ||
| JP2867547B2 (ja) | 導電突起の形成方法 | |
| JP3021509B2 (ja) | 導電突起の形成方法 |