JPH0474863B2 - - Google Patents
Info
- Publication number
- JPH0474863B2 JPH0474863B2 JP62271137A JP27113787A JPH0474863B2 JP H0474863 B2 JPH0474863 B2 JP H0474863B2 JP 62271137 A JP62271137 A JP 62271137A JP 27113787 A JP27113787 A JP 27113787A JP H0474863 B2 JPH0474863 B2 JP H0474863B2
- Authority
- JP
- Japan
- Prior art keywords
- mounting
- circuit board
- electrode
- protruding
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004020 conductor Substances 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 description 23
- 239000010410 layer Substances 0.000 description 15
- 238000000206 photolithography Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 2
- 238000002594 fluoroscopy Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Wire Bonding (AREA)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62271137A JPH01112743A (ja) | 1987-10-27 | 1987-10-27 | Ic実装用回路基板 |
| DE3817600A DE3817600C2 (de) | 1987-05-26 | 1988-05-24 | Verfahren zur Herstellung einer Halbleitervorrichtung mit einem keramischen Substrat und einem integrierten Schaltungskreis |
| FR8806997A FR2617335B1 (fr) | 1987-05-26 | 1988-05-26 | Substrat de connexion en ceramique muni de protuberances de raccordement a la pastille de circuit integre |
| US07/504,028 US5126818A (en) | 1987-05-26 | 1990-04-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62271137A JPH01112743A (ja) | 1987-10-27 | 1987-10-27 | Ic実装用回路基板 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01112743A JPH01112743A (ja) | 1989-05-01 |
| JPH0474863B2 true JPH0474863B2 (enrdf_load_stackoverflow) | 1992-11-27 |
Family
ID=17495831
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62271137A Granted JPH01112743A (ja) | 1987-05-26 | 1987-10-27 | Ic実装用回路基板 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01112743A (enrdf_load_stackoverflow) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005347299A (ja) | 2004-05-31 | 2005-12-15 | Shinko Electric Ind Co Ltd | チップ内蔵基板の製造方法 |
-
1987
- 1987-10-27 JP JP62271137A patent/JPH01112743A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01112743A (ja) | 1989-05-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7161242B2 (en) | Semiconductor device, semiconductor device substrate, and manufacturing method thereof that can increase reliability in mounting a semiconductor element | |
| KR100595885B1 (ko) | 반도체장치 및 그 제조방법 | |
| JP3258764B2 (ja) | 樹脂封止型半導体装置の製造方法ならびに外部引出用電極およびその製造方法 | |
| KR100264479B1 (ko) | 범프전극의 구조와 그 형성방법 | |
| EP0690490B1 (en) | Method of making a flip chip using electrically conductive polymers and dielectrics | |
| US4466181A (en) | Method for mounting conjoined devices | |
| US6236112B1 (en) | Semiconductor device, connecting substrate therefor, and process of manufacturing connecting substrate | |
| JP2002134545A (ja) | 半導体集積回路チップ及び基板、並びにその製造方法 | |
| JP2001127240A (ja) | 半導体装置の製造方法 | |
| TW201407737A (zh) | 具有內建定位件、中介層、以及增層電路之複合線路板 | |
| CN101276809A (zh) | 半导体器件及其制造方法 | |
| US11315848B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
| JPS62230027A (ja) | 半導体装置の製造方法 | |
| JP2001156203A (ja) | 半導体チップ実装用プリント配線板 | |
| JPH09129669A (ja) | 半導体のチップと基板間の電気的連結構造 | |
| JP2951882B2 (ja) | 半導体装置の製造方法及びこれを用いて製造した半導体装置 | |
| JPH0425038A (ja) | 半導体装置およびその製造方法ならびに半導体装置を用いた電子回路装置 | |
| JPH0474863B2 (enrdf_load_stackoverflow) | ||
| JP2002151801A (ja) | 回路基板構造およびその製造方法 | |
| JP3598189B2 (ja) | チップサイズパッケージ、その製造方法、およびその実装位置合わせの方法 | |
| JPH0410635A (ja) | フリップチップ実装方法 | |
| JPH0786340A (ja) | 半導体素子の接続方法 | |
| JP2002064177A (ja) | 半導体素子およびその製造方法 | |
| JP2652222B2 (ja) | 電子部品搭載用基板 | |
| JPH05251513A (ja) | 半導体装置 |