JPS5932172A - シヨツトキ−障壁ｍｏｓデバイスからなる集積回路及びその製造方法 - Google Patents

シヨツトキ−障壁ｍｏｓデバイスからなる集積回路及びその製造方法

Info

Publication number
JPS5932172A
JPS5932172A JP58133026A JP13302683A JPS5932172A JP S5932172 A JPS5932172 A JP S5932172A JP 58133026 A JP58133026 A JP 58133026A JP 13302683 A JP13302683 A JP 13302683A JP S5932172 A JPS5932172 A JP S5932172A
Authority
JP
Japan
Prior art keywords
region
channel
electrode
source
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58133026A
Other languages
English (en)
Japanese (ja)
Inventor
コンラツド　ジヨゼ　コエネイク
マーチン　ポール　レプセルター
ウイリアム　トーマス　リンチ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of JPS5932172A publication Critical patent/JPS5932172A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28537—Deposition of Schottky electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/378—Contact regions to the substrate regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor
    • H10D64/647—Schottky drain or source electrodes for IGFETs

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Power Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
JP58133026A 1982-07-23 1983-07-22 シヨツトキ−障壁ｍｏｓデバイスからなる集積回路及びその製造方法 Pending JPS5932172A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US401,142 1982-07-23
US06/401,142 US4485550A (en) 1982-07-23 1982-07-23 Fabrication of schottky-barrier MOS FETs

Publications (1)

Publication Number Publication Date
JPS5932172A true JPS5932172A (ja) 1984-02-21

Family

ID=23586485

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58133026A Pending JPS5932172A (ja) 1982-07-23 1983-07-22 シヨツトキ−障壁ｍｏｓデバイスからなる集積回路及びその製造方法

Country Status (6)

Country Link
US (1) US4485550A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS5932172A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CA (1) CA1215476A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3326534A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
FR (1) FR2530867B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB (1) GB2124428B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62122170A (ja) * 1985-11-21 1987-06-03 Nec Corp Ｍｉｓトランジスタ及びその製造方法
US7358550B2 (en) 2004-03-26 2008-04-15 Kabushiki Kaisha Toshiba Field effect transistor
JP2011519152A (ja) * 2008-04-11 2011-06-30 サントル ナシオナル ドゥ ラ ルシェルシェサイアンティフィク（セエヌエールエス） 相補型ｐ、及びｎＭＯＳＦＥＴトランジスタの製造方法、このトランジスタを包含する電子デバイス、及び少なくとも１つのこのデバイスを包含するプロセッサ
JP5328775B2 (ja) * 2008-04-21 2013-10-30 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法

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JPS6063926A (ja) * 1983-08-31 1985-04-12 Fujitsu Ltd 半導体装置の製造方法
JPS6072272A (ja) * 1983-09-28 1985-04-24 Toshiba Corp 半導体装置の製造方法
US4679303A (en) * 1983-09-30 1987-07-14 Hughes Aircraft Company Method of fabricating high density MOSFETs with field aligned channel stops
US4587710A (en) * 1984-06-15 1986-05-13 Gould Inc. Method of fabricating a Schottky barrier field effect transistor
US4641417A (en) * 1984-06-25 1987-02-10 Texas Instruments Incorporated Process for making molybdenum gate and titanium silicide contacted MOS transistors in VLSI semiconductor devices
US5098854A (en) * 1984-07-09 1992-03-24 National Semiconductor Corporation Process for forming self-aligned silicide base contact for bipolar transistor
WO1986001641A1 (en) * 1984-08-24 1986-03-13 American Telephone & Telegraph Company Mos transistors having schottky layer electrode regions and method of their production
US4728998A (en) * 1984-09-06 1988-03-01 Fairchild Semiconductor Corporation CMOS circuit having a reduced tendency to latch
JPH0697693B2 (ja) * 1984-12-05 1994-11-30 株式会社東芝 Ｍｏｓ型ｆｅｔのゲート構造の製造方法
US4635347A (en) * 1985-03-29 1987-01-13 Advanced Micro Devices, Inc. Method of fabricating titanium silicide gate electrodes and interconnections
US4632713A (en) * 1985-07-31 1986-12-30 Texas Instruments Incorporated Process of making Schottky barrier devices formed by diffusion before contacting
US4974046A (en) * 1986-07-02 1990-11-27 National Seimconductor Corporation Bipolar transistor with polysilicon stringer base contact
US5063168A (en) * 1986-07-02 1991-11-05 National Semiconductor Corporation Process for making bipolar transistor with polysilicon stringer base contact
US4732865A (en) * 1986-10-03 1988-03-22 Tektronix, Inc. Self-aligned internal mobile ion getter for multi-layer metallization on integrated circuits
ATE74466T1 (de) * 1988-03-10 1992-04-15 Asea Brown Boveri Mos-gesteuerter thyristor (mct).
JPH027571A (ja) * 1988-06-27 1990-01-11 Nissan Motor Co Ltd 半導体装置
US4920399A (en) * 1988-09-12 1990-04-24 Linear Integrated Systems, Inc. Conductance-modulated integrated transistor structure
US5338698A (en) * 1992-12-18 1994-08-16 International Business Machines Corporation Method of fabricating an ultra-short channel field effect transistor
US6624493B1 (en) 1994-05-31 2003-09-23 James D. Welch Biasing, operation and parasitic current limitation in single device equivalent to CMOS, and other semiconductor systems
US20040004262A1 (en) * 1994-05-31 2004-01-08 Welch James D. Semiconductor devices in compensated semiconductor
US6091128A (en) * 1994-05-31 2000-07-18 Welch; James D. Semiconductor systems utilizing materials that form rectifying junctions in both N and P-type doping regions, whether metallurgically or field induced, and methods of use
US6268636B1 (en) 1994-05-31 2001-07-31 James D. Welch Operation and biasing for single device equivalent to CMOS
US5760449A (en) * 1994-05-31 1998-06-02 Welch; James D. Regenerative switching CMOS system
US5663584A (en) * 1994-05-31 1997-09-02 Welch; James D. Schottky barrier MOSFET systems and fabrication thereof
JP3093620B2 (ja) * 1995-10-19 2000-10-03 日本電気株式会社 半導体装置の製造方法
US5889331A (en) * 1996-12-31 1999-03-30 Intel Corporation Silicide for achieving low sheet resistance on poly-Si and low Si consumption in source/drain
US6683362B1 (en) 1999-08-24 2004-01-27 Kenneth K. O Metal-semiconductor diode clamped complementary field effect transistor integrated circuits
US6303479B1 (en) * 1999-12-16 2001-10-16 Spinnaker Semiconductor, Inc. Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts
US20030235936A1 (en) * 1999-12-16 2003-12-25 Snyder John P. Schottky barrier CMOS device and method
JP3833903B2 (ja) * 2000-07-11 2006-10-18 株式会社東芝 半導体装置の製造方法
US6544888B2 (en) * 2001-06-28 2003-04-08 Promos Technologies, Inc. Advanced contact integration scheme for deep-sub-150 nm devices
US20060079059A1 (en) * 2001-08-10 2006-04-13 Snyder John P Transistor having high dielectric constant gate insulating layer and source and drain forming schottky contact with substrate
EP1417718A1 (en) * 2001-08-10 2004-05-12 Spinnaker Semiconductor, Inc. Transistor having high dielectric constant gate insulating layer and source and drain forming schottky contact with substrate
US6974737B2 (en) * 2002-05-16 2005-12-13 Spinnaker Semiconductor, Inc. Schottky barrier CMOS fabrication method
US7902029B2 (en) * 2002-08-12 2011-03-08 Acorn Technologies, Inc. Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor
US7176483B2 (en) * 2002-08-12 2007-02-13 Acorn Technologies, Inc. Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US6833556B2 (en) * 2002-08-12 2004-12-21 Acorn Technologies, Inc. Insulated gate field effect transistor having passivated schottky barriers to the channel
US7084423B2 (en) 2002-08-12 2006-08-01 Acorn Technologies, Inc. Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
WO2005029583A2 (en) * 2003-09-19 2005-03-31 Spinnaker Semiconductor, Inc. Schottky barrier integrated circuit
JP2005209782A (ja) * 2004-01-21 2005-08-04 Toshiba Corp 半導体装置
US20070001223A1 (en) * 2005-07-01 2007-01-04 Boyd Diane C Ultrathin-body schottky contact MOSFET
US7250666B2 (en) * 2005-11-15 2007-07-31 International Business Machines Corporation Schottky barrier diode and method of forming a Schottky barrier diode
US7709924B2 (en) * 2007-07-16 2010-05-04 International Business Machines Corporation Semiconductor diode structures
US9748356B2 (en) 2012-09-25 2017-08-29 Stmicroelectronics, Inc. Threshold adjustment for quantum dot array devices with metal source and drain
US9601630B2 (en) 2012-09-25 2017-03-21 Stmicroelectronics, Inc. Transistors incorporating metal quantum dots into doped source and drain regions
US10002938B2 (en) 2013-08-20 2018-06-19 Stmicroelectronics, Inc. Atomic layer deposition of selected molecular clusters
US9620611B1 (en) 2016-06-17 2017-04-11 Acorn Technology, Inc. MIS contact structure with metal oxide conductor
DE112017005855T5 (de) 2016-11-18 2019-08-01 Acorn Technologies, Inc. Nanodrahttransistor mit Source und Drain induziert durch elektrische Kontakte mit negativer Schottky-Barrierenhöhe
US11362215B2 (en) * 2018-03-30 2022-06-14 Intel Corporation Top-gate doped thin film transistor

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JPS51120674A (en) * 1975-04-16 1976-10-22 Hitachi Ltd Semiconductor device
JPS5515263A (en) * 1978-07-19 1980-02-02 Chiyou Lsi Gijutsu Kenkyu Kumiai Mos type semiconductor device

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JPS51120674A (en) * 1975-04-16 1976-10-22 Hitachi Ltd Semiconductor device
JPS5515263A (en) * 1978-07-19 1980-02-02 Chiyou Lsi Gijutsu Kenkyu Kumiai Mos type semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62122170A (ja) * 1985-11-21 1987-06-03 Nec Corp Ｍｉｓトランジスタ及びその製造方法
US7358550B2 (en) 2004-03-26 2008-04-15 Kabushiki Kaisha Toshiba Field effect transistor
CN100446271C (zh) * 2004-03-26 2008-12-24 株式会社东芝 场效应晶体管
US7479674B2 (en) 2004-03-26 2009-01-20 Kabushiki Kaisha Toshiba Field effect transistor
JP2011519152A (ja) * 2008-04-11 2011-06-30 サントル ナシオナル ドゥ ラ ルシェルシェサイアンティフィク（セエヌエールエス） 相補型ｐ、及びｎＭＯＳＦＥＴトランジスタの製造方法、このトランジスタを包含する電子デバイス、及び少なくとも１つのこのデバイスを包含するプロセッサ
JP5328775B2 (ja) * 2008-04-21 2013-10-30 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法

Also Published As

Publication number Publication date
GB2124428B (en) 1986-03-05
DE3326534C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-03-04
CA1215476A (en) 1986-12-16
GB8319569D0 (en) 1983-08-24
FR2530867A1 (fr) 1984-01-27
DE3326534A1 (de) 1984-01-26
GB2124428A (en) 1984-02-15
FR2530867B1 (fr) 1988-12-09
US4485550A (en) 1984-12-04

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