JPS59198746A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS59198746A
JPS59198746A JP58073469A JP7346983A JPS59198746A JP S59198746 A JPS59198746 A JP S59198746A JP 58073469 A JP58073469 A JP 58073469A JP 7346983 A JP7346983 A JP 7346983A JP S59198746 A JPS59198746 A JP S59198746A
Authority
JP
Japan
Prior art keywords
film
aluminum
wiring layer
pattern
bonding pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58073469A
Other languages
English (en)
Inventor
Shinji Sugaya
慎二 菅谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58073469A priority Critical patent/JPS59198746A/ja
Publication of JPS59198746A publication Critical patent/JPS59198746A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05553Shape in top view being rectangular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 (al  発明の技術分野 本発明は半導体装置のうち、特に半導体チップ面に設け
る導電配線層の構成に関する。
(b)従来技術と問題点 周知のように、半導体集積回路(IC)においては半導
体チップに半導体素子が多数形成されて、チップ面上に
これらを相互に接続するための導電配線層と、外部導出
用のボンディングワイヤを接着するポンディングパッド
部とが設けられている。
このような配線層およびポンディングパッド部の導電材
料としてはアルミニウム(AI)あるいはアルミニウム
シリコン(AI−3t)が最も良く使用されており、そ
れは電気伝導度が比較的良くて且つ安価に得られるため
である。また、アルミニウムシリコンはシリコン含有量
が1%前後で、これはシリコン基板や二酸化シリコン(
Si02 ) l1jt’との接着力を強くするための
ものである。
一方、ICはLSI、VLSIと高集積化されてきてお
り、それに伴って配線層も設計上から許容限度の近くま
で細くした配線パターンが形成されて、高密度化されて
いる。従って、配線層に若干の欠陥があればその部分で
マイグレーション(粒子移動)を起こして断線する可能
性が著しく増加してきた。
ところで、導電配線材料としてアルミニウムに11((
:u)を1〜5%程度含ませたアルミニウム銅合金を利
用する方法が知られており、アルミニウム銅合金はアル
ミニウム、アルミニウムシリコンより優れた電気伝導性
をもっているから、アルミニウム銅合金を用いると伝導
性が良くなって欠陥部分からの断線も減少するメリット
がある。しかし、アルミニウム銅合金膜でポンディング
パッド部を形成すると、硬度が高くなるためにポンディ
ングワイヤ(アルミニウム線または金線)とのポンディ
ングによる接着強度が弱くなって、その部分で断線しや
すい問題が起きる。
(C)発明の目的 本発明はこのような矛盾した問題点を取り除いた配線構
造を有する半導体装置を提案するものである。
(dl  発明の構成 その目的は、半導体チップ上に設けるポンディングパッ
ト部の導電膜をアルミニウム膜あるいはアルミニウムシ
リコン膜とし、素子間の接続および素子とポンディング
バンド部との接続をおこなう導電配線層をアルミニウム
銅合金膜とした半導体装置によって達成される。
(el  発明の実施例 以下1図面を参照して実施例によって詳細に説明する。
第1図は本発明にかかる半導体チップの部分平面図を示
しており、1はアルミニウム膜あるいはアルミニウムシ
リコン膜からなるボンディングバンド部、2はアルミニ
ウム銅合金膜からなる配線N(導電配線層)、3はポン
ディングしたアルミニウムワイヤである。また、第2図
はその部分断面図を示し、4はシリコン基板、5ば5i
02膜(絶縁膜)である。
従来は、例えばアルミニウムシリコン膜でポンディング
パッド部と配線層とをすべて形成していたが、上記した
ような本発明にかかる構造に構成すると、ボンディング
バンド部1には柔らかいアルミニウム膜あるいはアルミ
ニウムシリコン膜が形成されていて、アルミニウムワイ
ヤ3と接着するため接着力が強固で、ワイヤの剥れはな
い。且つ、配線層2はアルミニウム銅合金膜でパターン
ニングされており、多少の欠陥ではマイグレーシヨンを
起こさず断線することがなくなる。従ってICは長寿命
化されて、信頼性が著しく向上することになる。
次に、かような構造の半導体装置の製造方法を説明する
。第3図ないし第9図はその工程順断面図で、第3図に
示すようにシリコン基板4の5iQ2膜5上にスパッタ
法または蒸着法で膜厚1μmのアルミニウムシリコン膜
6を被着する。次いで、第4図に示すようにポンディン
グパッド部1を被覆するレジスト膜パターン7を形成し
た後、第5図に示すようにリアクティブイオンエツチン
グによって露出したアルミニウムシリコン膜6を除去し
て、ポンディングパッド部工のみアルミニウムシリコン
膜6を残存させる。
次いで、第6図に示すようにレジスト膜パターン7の上
からスパッタ法または蒸着法で膜厚1μmのアルミニウ
ム銅合金膜8を被着する。次いで、第7図に示すように
レジスト膜パターン7を/8解除去して、同時にレジス
ト膜パターン上のアルミニウム銅合金膜8をリフトオフ
によって除去する。次いで、第8図に示すようにポンデ
ィングパッド部1を含む配線層2をマスクするレジスト
膜パターン9を形成した後、露出部をエツチングして第
9図に示すようなポンディングパッド部1と配線層2と
をパターンニングする。このようにすれば、本発明にか
かる半導体装置の配線構造が完成される。
尚、かような製造法に代わり、予めアルミニウム銅合金
膜でポンディングパッド部を含む配線層パターンを形成
し、次いでボンディングバンド部のみアルミニウムシリ
コン膜パターンを積み重ねる方法が想定される。然し、
その方法はパターンユング後の配線層の導電性回復のた
めの低温熱処理によってホンディングバンド部表面にも
銅が混入されることになり、硬度が上るから従来と同様
にワイヤの剥れが起きる。従って、上記のような製造方
法を採ることが必要である。
(fl  発明の効果 以上の説明から明らかなように、本発明によれば断線の
恐れが減少した導電配線層が得られ、且つボンデングワ
イヤの剥れの心配もなくなるから、ICの信頼性は極め
て向上するものである。
【図面の簡単な説明】
第1図は本発明にかかる半導体チ・ノブの部分平面図、
第2図はその部分断面図、第3図〜第9図は本発明の製
造工程順断面図である。 図中、1はポンデイングパ・ンド部、  2Lよ西己李
泉層(導電配線層)、3はアルミニウム銅イ−?、  
44よシリコン基板、5は5i02膜、6はアルミニウ
ムシリコン膜、7,9はレジスト膜ノ々クーン、8(ま
アルミニウム銅合金膜を示してしする。 第1図 第3図 第5図 第6図 第7図 第8図 第9図

Claims (1)

    【特許請求の範囲】
  1. 半導体チ・7プ上に設けるポンディングパッド部の導電
    膜をアルミニウム膜あるいはアルミニウムシリコン膜と
    し、素子間の接続および素子とポンディングパッド部と
    の接続をおこなう導電配線層をアルミニウム銅合金膜と
    したことを特徴とす葛半導体装置。
JP58073469A 1983-04-25 1983-04-25 半導体装置 Pending JPS59198746A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58073469A JPS59198746A (ja) 1983-04-25 1983-04-25 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58073469A JPS59198746A (ja) 1983-04-25 1983-04-25 半導体装置

Publications (1)

Publication Number Publication Date
JPS59198746A true JPS59198746A (ja) 1984-11-10

Family

ID=13519159

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58073469A Pending JPS59198746A (ja) 1983-04-25 1983-04-25 半導体装置

Country Status (1)

Country Link
JP (1) JPS59198746A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5003373A (en) * 1987-11-30 1991-03-26 Mitsubishi Denki Kabushiki Kaisha Structure of electrode junction for semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5003373A (en) * 1987-11-30 1991-03-26 Mitsubishi Denki Kabushiki Kaisha Structure of electrode junction for semiconductor device

Similar Documents

Publication Publication Date Title
US5010389A (en) Integrated circuit substrate with contacts thereon for a packaging structure
JPS5851425B2 (ja) ハンドウタイソウチ
US5309025A (en) Semiconductor bond pad structure and method
JPS62145758A (ja) パラジウムを用いる銅製ボンデイングパツドの酸化防止法
JPS59198746A (ja) 半導体装置
JPH06224200A (ja) 集積半導体デバイスおよび集積半導体デバイス上にバンプ構造を形成する方法
JPH0722461A (ja) 同軸フリップチップ接続構造およびその形成方法
JPH08222571A (ja) フリップチップicとその製造方法
JPH03218644A (ja) 回路基板の接続構造
JPS63318742A (ja) 半導体集積回路装置及びその製造方法
JPS6348427B2 (ja)
JPH03268385A (ja) はんだバンプとその製造方法
JPH10209154A (ja) 半導体装置
JPS62136857A (ja) 半導体装置の製造方法
JPH03132036A (ja) 半導体装置の製造方法
JPS60140737A (ja) 半導体装置の製造方法
JPH09172019A (ja) 下地電極の形成方法
KR100876286B1 (ko) 반도체 소자 및 그 제조 방법
JPH02140955A (ja) 半導体装置
JPH0344933A (ja) 半導体装置
JPH0469427B2 (ja)
JPS63252445A (ja) 半導体装置の製造方法
JPH03171732A (ja) 半導体装置
JPS63257268A (ja) 半導体集積回路
JPH0344935A (ja) 半導体装置