JPS59134857A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS59134857A
JPS59134857A JP58008137A JP813783A JPS59134857A JP S59134857 A JPS59134857 A JP S59134857A JP 58008137 A JP58008137 A JP 58008137A JP 813783 A JP813783 A JP 813783A JP S59134857 A JPS59134857 A JP S59134857A
Authority
JP
Japan
Prior art keywords
island
net
resin
semiconductor element
edge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58008137A
Other languages
English (en)
Inventor
Hisaharu Sakurai
桜井 寿春
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58008137A priority Critical patent/JPS59134857A/ja
Publication of JPS59134857A publication Critical patent/JPS59134857A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201Structure
    • H01L2224/32012Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32013Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置に関する。
〔発明の技術的背景〕
従来の半導体装置の一例は第1図に示す如くで、アイラ
ンド部/aおよびリード部/bを有するリードフレーム
lと、アイランド部/a上に載置された半導体素子コと
、半導体素子a上の電極とリード部/1)とを接続する
細線、例えば金ワイヤ3と、アイランド部/a、半導体
素子コおよび細線3をモールドする樹脂ダとを備えてい
る。
〔背景技術の問題点〕
しかるに、従来の半導体装置では、牛導体素子コが大型
化し、特に!r m”以上のものでは1図示のように、
マイクロクログクSが発生し、熱サイクル疲労を加える
とクラックが成長し、底面に達する到るものである。こ
れは、リードフレーム/の材料であるQアロイ(Niが
ダ2チ、残部がFeと微量の添加物からなる)と樹脂ダ
の材料との熱膨張率の差から生ずる応力がアイランド縁
部に集中するために起こる。クラックが底面にまで達す
ると、水分が侵入し、耐湿性が弱くなる等の問題がある
。このような問題は、樹脂ダとして、高熱伝導性のもの
が要求される場合に特に深刻であった。
高熱伝導性の樹脂は一般に熱膨張率が大きく、従ってク
ラックの発生がおきやすいからである。
〔発明の目的〕
本発明の目的は、樹脂部のクラックが生じにくい半導体
装置を提供することにある。
〔発明の概要〕
本発明の半導体装置は、アイランド部の下面に。
該下面の周縁部から縁部が突出するように金属またはガ
ラスのメツシーを接合したものである。
〔発明の実施例〕
第2図は1本発明の一実施例を示すものである7この実
施例の半導体装置は、第1図のものと同様。
アイランド部/aおよびリード部lbを有するリードフ
レームlと、アイランド部la上に載置された半導体素
子コと、半導体素子コ上の電極とリード部/bとを接続
する細線1例えば金ワイヤ3と、アイランド部/a、半
導体素子λおよび細線3をモールドする樹脂グとを備え
ているほか9図示のように、アイランド部/aの下面に
、縁部6aがアイランド部/への周縁部/cから突出す
るように接着剤または半田により接合されたメッシュメ
、7シユ6の縁部6aの、アイランド部/a周縁部/c
からの突出長は例えば/ltrm程度とする。
このメツジュロは、太さθ、/〜θ、S−程度の単線ま
たはより線を第3図に示すように編んだものである。
メツシュの材料としては、樹脂との熱膨張率の差が小さ
いアルミニウム、銅等がよいがガラス等の絶縁材料を用
いてもよい。
メツジュロのアイランド部乙の下面への接合は。
アイランド部/aに素子λを載置する前でも、後でもよ
く、またワイヤ、ポンディ7グ(細線3の接続)より後
でもよい。
このような構造の半導体装置では、樹脂lがメツシー6
の編み目や先端部の線間のすきまにまわり込み、それぞ
れの部所で応力分散が行なわれる。
このため、クラックの発生が抑制される。
第グ図は、本発明の他の実施例を示すものである。この
実施例では、メツジュロとして、ガラスクロスで形成さ
れ、アイランド部/aの下面を覆うのみならずリード部
/bに達する拡がりを持ち、リード部/bにも接合され
ているものが用いられている。
〔発明の効果〕
以上のように、本発明では、アイランド部/aの下面に
、縁部が突出するメ1.シーを接合したので、クラ2り
の発生を抑制することができる。従って、樹脂として、
熱膨張率の大きい高熱伝導性のものを用いることについ
ての制約(クラ、7りの発生がなくなる。また、メツシ
ュとして銅、アルミニウム等高熱伝導性の材料のものを
用いれば、半導体素子ユからの熱発散がさらに良好にな
る。
【図面の簡単な説明】
第1図は従来の半導体装置の一例を示す断面図。 第2図は本発明の半導体装置の一実施例を示す断面図、
第3図は本発明で用いられるメツシーの一例を示す図、
第7図は本発明の他の実施例を示す断面図である。 l・・・リードフレーム−/a・・・アイランド部、/
b・・・リード部、ユ・・・半導体素子、3・・・細線
、t・・・m脂、−1−・・−クラ1.り、乙・・・メ
ツシシュ。

Claims (1)

    【特許請求の範囲】
  1. アイランド部およびリード部を有するリードフレームと
    、前記アイランド部上に載置された半導体素子と2該半
    導体素子上の電極と前記リード部とを接続する細線と、
    前記アイランド部、半導体素子および前記細線をモール
    ドする樹脂部とを備える半導体装置において、前記アイ
    ランド部の下面に前記下面の周縁部から縁部が突出する
    ように金属またはガラスのメツシュを接合したことを特
    徴とする半導体装置。
JP58008137A 1983-01-21 1983-01-21 半導体装置 Pending JPS59134857A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58008137A JPS59134857A (ja) 1983-01-21 1983-01-21 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58008137A JPS59134857A (ja) 1983-01-21 1983-01-21 半導体装置

Publications (1)

Publication Number Publication Date
JPS59134857A true JPS59134857A (ja) 1984-08-02

Family

ID=11684901

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58008137A Pending JPS59134857A (ja) 1983-01-21 1983-01-21 半導体装置

Country Status (1)

Country Link
JP (1) JPS59134857A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6370548A (ja) * 1986-09-12 1988-03-30 Mitsubishi Electric Corp 半導体装置用リ−ドフレ−ム
JPS63142855U (ja) * 1987-03-11 1988-09-20
JPS6418734U (ja) * 1987-07-23 1989-01-30

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6370548A (ja) * 1986-09-12 1988-03-30 Mitsubishi Electric Corp 半導体装置用リ−ドフレ−ム
JPH0545063B2 (ja) * 1986-09-12 1993-07-08 Mitsubishi Electric Corp
JPS63142855U (ja) * 1987-03-11 1988-09-20
JPH0526760Y2 (ja) * 1987-03-11 1993-07-07
JPS6418734U (ja) * 1987-07-23 1989-01-30

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