JPH01319955A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH01319955A
JPH01319955A JP63154446A JP15444688A JPH01319955A JP H01319955 A JPH01319955 A JP H01319955A JP 63154446 A JP63154446 A JP 63154446A JP 15444688 A JP15444688 A JP 15444688A JP H01319955 A JPH01319955 A JP H01319955A
Authority
JP
Japan
Prior art keywords
semiconductor device
height
wire
semiconductor
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63154446A
Other languages
English (en)
Inventor
Yoshiichi Saito
斎藤　由一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP63154446A priority Critical patent/JPH01319955A/ja
Publication of JPH01319955A publication Critical patent/JPH01319955A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の薄型化と半導体装置の素材の大
径化に対応し、半導体装置自体の機械的強度を確保しつ
つ薄型化を図る上で問題となる接続線のループ高さを低
くする事ができる半導体装置に関するものである。
〔従来の技術〕
従来、半導体装置の素材の径が小さい場合は、それを薄
くするために回転する砥石や研磨剤によって素材の裏面
全体を研削する方法を用いていた。また、半導体の接続
線のループ高さを低くするために半導体チップを搭載す
るフレームにデインプル加工を施し外部端子用のフレー
ム面よりも低くする技術がある。
〔発明が解決しようとする課題〕
上述した従来の半導体装置の構造では、素材の径が小さ
い場合にはそれを薄く研削していっても割れるなどの問
題はなかったが、近年、素材の大口径化が進み、一方で
は電子部品全般の薄型化が要求される中で、大口径の半
導体装置を薄く研削していくと、反りや割などの問題が
発生していた。
このため一定限度の厚さ以下に研削する事ができず、そ
れ放生導体装置と外部端子とを接続する金属ワイヤーの
ループ高さまで含めた高さが低く出来ないという欠点が
あった。
一方、フレームのデインプル加工の場合でもフレームが
平坦でないために、フレームを送る場合に、引っかかり
が発生し、リードが曲ったり、加熱した時に均一に熱が
伝わらず半導体装置との接続が充分に行なえない等の欠
点があった。
〔発明の従来技術に対する相違点〕
上述した従来の半導体装置の薄型化の技術に対し、本発
明は、半導体装置用素材の大口径化に対応し、半導体装
置の一部分の厚さを従来通りとして機械的強度を確保し
つつ、外部端子との接続線を被着する部分だけを一段低
い領域に形成する事によって、接続線のループ高さも含
めた半導体装置の全高を低く出来るという相違点を有す
る。
〔課題を解決するための手段〕
本発明の半導体装置は半導体の電気的性能を発揮する機
能部分ａと、外部端子との接続ワイヤーとの接着部分の
領域すとがあり、ｂの領域がａの領域よりも一段低く形
成する構造を有している。
また、ａの素子領域とｂの接続部分の領域との間は、配
線が断線しにくい様になだらか傾斜をつけである。この
様な構造のため、外部端子との接続用の金属線をａ領域
よりも一段低いｂ領域に接着する為接続線のループ高さ
が低く出来る様になっている。
〔実施例〕
次に、本発明について図面を参照して説明する。
第１図は、本発明の一実施例の縦断面図である。
半導体チップ１は、外部端子２との電気的接続用のワイ
ヤー３の接着部分を、半導体チップ１の外周部に１００
〜２００μｍ低く形成した例である。このため接続用ワ
イヤー３のループ高さが従来の構造のものより１００〜
２００μ低くすることが可能となる。
第２図は、本発明の実施例２の縦断面図である。
この場合は、半導体チップ３の外周部だけを１００〜２
００μｍ高い構造とし、半導体チップの中央部を薄く形
成した例である。この場合にも接続用ワイヤー３のルー
プ高さを低くすることができ、外周部の３００μｍ以上
の厚い部分によって機械的強度を確保し、半導体素材を
２００μｍ以下に研削した場合などに発生する割れや反
りを防止できるという利点がある。
〔発明の効果〕
以上説明したように、本発明は、半導体装置の中で外部
端子との接続用ワイヤーを接着する領域を、他の部分よ
りも一段低くした構造にする事により、ワイヤーのルー
プ高さを低く抑える事ができ、その結果半導体装置の全
高を低くできる効果がある。また、近年の半導体用素材
の大口径化に対応し、２００μｍ以下に薄く研削しても
機械的強度を確保するための厚い領域があるために、素
材の割れなどのロスを大幅に低減する事が可能となると
いう効果がある。
また、このような半導体チップ自体の改良によって、デ
インプル加工などの特殊な処理を施したフレームを使用
する必要がないために、リード曲りなどのトラブルもな
く、コスト的にも有利である。
【図面の簡単な説明】
第１図は、本発明の実施例１の縦断面図であり、第２図
は、実施例２の縦断面図である。 １・・・・・・半導体チップ、２・・・・・・外部端子
、３・・・・・・接続用ワイヤー、４・・・・・・半導
体チップ搭載用フレーム 代理人　弁理士　　内　原　　　音 粥Ｚ図

Claims (1)

    【特許請求の範囲】
  1. 　半導体装置から外部端子へ接続するための接続用ワイ
    ヤーを接着する領域を半導体装置の他の領域よりも一段
    低く作る事を特徴とした半導体装置。
JP63154446A 1988-06-21 1988-06-21 半導体装置 Pending JPH01319955A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63154446A JPH01319955A (ja) 1988-06-21 1988-06-21 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63154446A JPH01319955A (ja) 1988-06-21 1988-06-21 半導体装置

Publications (1)

Publication Number Publication Date
JPH01319955A true JPH01319955A (ja) 1989-12-26

Family

ID=15584388

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63154446A Pending JPH01319955A (ja) 1988-06-21 1988-06-21 半導体装置

Country Status (1)

Country Link
JP (1) JPH01319955A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5341027A (en) * 1991-11-14 1994-08-23 Samsung Electronics Co., Ltd. Semiconductor chip having notches formed in peripheral edges thereof
US5606198A (en) * 1993-10-13 1997-02-25 Yamaha Corporation Semiconductor chip with electrodes on side surface

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5341027A (en) * 1991-11-14 1994-08-23 Samsung Electronics Co., Ltd. Semiconductor chip having notches formed in peripheral edges thereof
US5606198A (en) * 1993-10-13 1997-02-25 Yamaha Corporation Semiconductor chip with electrodes on side surface

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