JPS59103366A - 半導体メモリ素子の製造方法 - Google Patents

半導体メモリ素子の製造方法

Info

Publication number
JPS59103366A
JPS59103366A JP57212462A JP21246282A JPS59103366A JP S59103366 A JPS59103366 A JP S59103366A JP 57212462 A JP57212462 A JP 57212462A JP 21246282 A JP21246282 A JP 21246282A JP S59103366 A JPS59103366 A JP S59103366A
Authority
JP
Japan
Prior art keywords
gate
layer
transistor
oxide film
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57212462A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6240869B2 (enExample
Inventor
Hideki Arakawa
秀貴 荒川
Hiromi Kawashima
川嶋　博美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57212462A priority Critical patent/JPS59103366A/ja
Priority to EP83307178A priority patent/EP0112078A3/en
Publication of JPS59103366A publication Critical patent/JPS59103366A/ja
Publication of JPS6240869B2 publication Critical patent/JPS6240869B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
JP57212462A 1982-12-03 1982-12-03 半導体メモリ素子の製造方法 Granted JPS59103366A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP57212462A JPS59103366A (ja) 1982-12-03 1982-12-03 半導体メモリ素子の製造方法
EP83307178A EP0112078A3 (en) 1982-12-03 1983-11-24 A semiconductor memory element and a method for manufacturing it

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57212462A JPS59103366A (ja) 1982-12-03 1982-12-03 半導体メモリ素子の製造方法

Publications (2)

Publication Number Publication Date
JPS59103366A true JPS59103366A (ja) 1984-06-14
JPS6240869B2 JPS6240869B2 (enExample) 1987-08-31

Family

ID=16623031

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57212462A Granted JPS59103366A (ja) 1982-12-03 1982-12-03 半導体メモリ素子の製造方法

Country Status (2)

Country Link
EP (1) EP0112078A3 (enExample)
JP (1) JPS59103366A (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3316096A1 (de) * 1983-05-03 1984-11-08 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von speicherzellen mit einem ein schwebendes gate aufweisenden mos-feldeffekttransistor
JPS61123169A (ja) * 1984-11-20 1986-06-11 Fujitsu Ltd 半導体集積回路
IT1196997B (it) * 1986-07-25 1988-11-25 Sgs Microelettronica Spa Processo per realizzare strutture includenti celle di memoria non volatili e2prom con strati di silicio autoallineate transistori associati
EP0782196A1 (en) * 1995-12-28 1997-07-02 STMicroelectronics S.r.l. Method of fabricating EEPROM memory devices and EEPROM memory device so formed

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4142926A (en) * 1977-02-24 1979-03-06 Intel Corporation Self-aligning double polycrystalline silicon etching process
JPS53124084A (en) * 1977-04-06 1978-10-30 Hitachi Ltd Semiconductor memory device containing floating type poly silicon layer and its manufacture
US4203158A (en) * 1978-02-24 1980-05-13 Intel Corporation Electrically programmable and erasable MOS floating gate memory device employing tunneling and method of fabricating same
US4477825A (en) * 1981-12-28 1984-10-16 National Semiconductor Corporation Electrically programmable and erasable memory cell

Also Published As

Publication number Publication date
JPS6240869B2 (enExample) 1987-08-31
EP0112078A3 (en) 1986-06-25
EP0112078A2 (en) 1984-06-27

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