JPS5843023A - タイミング制御方式 - Google Patents
タイミング制御方式Info
- Publication number
- JPS5843023A JPS5843023A JP56139757A JP13975781A JPS5843023A JP S5843023 A JPS5843023 A JP S5843023A JP 56139757 A JP56139757 A JP 56139757A JP 13975781 A JP13975781 A JP 13975781A JP S5843023 A JPS5843023 A JP S5843023A
- Authority
- JP
- Japan
- Prior art keywords
- timing
- data
- clock
- transfer
- data transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Complex Calculations (AREA)
- Information Transfer Systems (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56139757A JPS5843023A (ja) | 1981-09-07 | 1981-09-07 | タイミング制御方式 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56139757A JPS5843023A (ja) | 1981-09-07 | 1981-09-07 | タイミング制御方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5843023A true JPS5843023A (ja) | 1983-03-12 |
JPS6120024B2 JPS6120024B2 (enrdf_load_stackoverflow) | 1986-05-20 |
Family
ID=15252673
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56139757A Granted JPS5843023A (ja) | 1981-09-07 | 1981-09-07 | タイミング制御方式 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5843023A (enrdf_load_stackoverflow) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63197312U (enrdf_load_stackoverflow) * | 1987-06-08 | 1988-12-19 | ||
JPS6433721U (enrdf_load_stackoverflow) * | 1987-08-25 | 1989-03-02 | ||
JPH0438020U (enrdf_load_stackoverflow) * | 1990-07-27 | 1992-03-31 |
-
1981
- 1981-09-07 JP JP56139757A patent/JPS5843023A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6120024B2 (enrdf_load_stackoverflow) | 1986-05-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3209776B2 (ja) | エミュレーション装置とそれに使用するマイクロコントローラ | |
US4615017A (en) | Memory controller with synchronous or asynchronous interface | |
US5280584A (en) | Two-way data transfer apparatus | |
US3715729A (en) | Timing control for a multiprocessor system | |
JPS5847050B2 (ja) | 入出力割込みシステム | |
US4330824A (en) | Universal arrangement for the exchange of data between the memories and the processing devices of a computer | |
US5537582A (en) | Bus interface circuitry for synchronizing central processors running at multiple clock frequencies to other computer system circuitry | |
JPS58222363A (ja) | 共用メモリの割振装置 | |
JPS63204942A (ja) | インタフェース | |
JPS5843023A (ja) | タイミング制御方式 | |
EP0337993B1 (en) | Parallel processing state alignment | |
GB2234372A (en) | Mass memory device | |
JPH0624908Y2 (ja) | デ−タ転送制御装置 | |
JPS59146361A (ja) | デユアルポ−トメモリ制御回路 | |
JP2645462B2 (ja) | データ処理システム | |
SU1257656A1 (ru) | Устройство дл сопр жени цифровой вычислительной машины с внешним устройством | |
JPS59189435A (ja) | デ−タ転送制御装置 | |
JPH0215425Y2 (enrdf_load_stackoverflow) | ||
JPH01114965A (ja) | プロセッサアレイヘのコマンド転送方式及び回路 | |
JPS6117031B2 (enrdf_load_stackoverflow) | ||
JP2661741B2 (ja) | 半導体記憶回路 | |
JPS62256160A (ja) | プロセツサ間レジスタの同時アクセス防止方式 | |
JPS61161560A (ja) | メモリ装置 | |
JPH055133B2 (enrdf_load_stackoverflow) | ||
JPS63182763A (ja) | 記憶装置制御方式 |